公开(公告)号：US07170794B2

公开(公告)日：2007-01-30

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US20050088879A1

公开(公告)日：2005-04-28

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US07184316B2

公开(公告)日：2007-02-27

申请号：US11038726

申请日：2005-01-19

申请人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

发明人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

摘要翻译： 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 将第二电压施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20050162925A1

公开(公告)日：2005-07-28

申请号：US11038726

申请日：2005-01-19

申请人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

发明人： In-Wook Cho ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Byou-Ree Lim ,  Sang-Su Kim

IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0425 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile memory cell array having common drain lines and method of operating the same are disclosed. A positive voltage is applied to a gate of a selected cell and gates of memory cells that share a word line with the selected cell. A first voltage is applied to a drain of the selected cell and drains of the memory cells that share at least a drain line with the selected cell. A second voltage is applied to a source of the selected cell and sources of memory cells that share a bit line with the selected cell, the second voltage being less than the first voltage, such that electrons are injected into the charge storage region of the selected cell to program. A third voltage, which is higher than the second voltage, is applied to bit lines that are not connected to the selected cell.

摘要翻译： 公开了一种具有共同漏极线的非易失性存储单元阵列及其操作方法。 将正电压施加到所选单元的栅极和与所选单元共享字线的存储单元的栅极。 将第一电压施加到所选择的单元的漏极和与所选择的单元共享至少漏极线的存储器单元的漏极。 第二电压被施加到所选择的单元的源和与所选择的单元共享位线的存储器单元的源，第二电压小于第一电压，使得电子被注入到所选择的单元的电荷存储区域中 单元格程序。 高于第二电压的第三电压被施加到未连接到所选择的单元的位线。

公开(公告)号：US20050067651A1

公开(公告)日：2005-03-31

申请号：US10944382

申请日：2004-09-16

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Byoung-Jin Lee ,  In-Wook Cho

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Byoung-Jin Lee ,  In-Wook Cho

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833

摘要： A nonvolatile memory cell employing a plurality of dielectric nanoclusters and a method of fabricating the same are disclosed. In one embodiment, the nonvolatile memory cell comprises a semiconductor substrate having a channel region. A control gate is disposed above the channel region. A control gate dielectric layer is disposed between the channel region and the control gate. A plurality of dielectric nanoclusters are disposed between the channel region and the control gate dielectric layer. Each nanocluster may be separated from adjacent nanoclusters by the control gate dielectric layer. A tunnel oxide layer is disposed between the plurality of dielectric nanoclusters and the channel region. Further, a source and a drain are formed in the semiconductor substrate.

摘要翻译： 公开了一种采用多个电介质纳米簇的非易失性存储单元及其制造方法。 在一个实施例中，非易失性存储单元包括具有沟道区的半导体衬底。 控制门设置在通道区域的上方。 控制栅介质层设置在沟道区和控制栅之间。 多个介电纳米团簇设置在沟道区和控制栅介质层之间。 每个纳米团簇可以通过控制栅极介电层与相邻的纳米团簇分离。 隧道氧化层设置在多个介电纳米簇与沟道区之间。 此外，在半导体衬底中形成源极和漏极。

公开(公告)号：US06878575B2

公开(公告)日：2005-04-12

申请号：US10727125

申请日：2003-12-03

申请人： Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

发明人： Jae-Yoon Yoo ,  Moon-Han Park ,  Byou-Ree Lim

IPC分类号： H01L21/31 ,  H01L21/28 ,  H01L21/314 ,  H01L29/51 ,  H01L21/335

CPC分类号： H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

摘要： Methods of preparing improved semiconductor substrates having gate oxide layers formed thereon, and use of such substrates in fabricating improved semiconductor devices, are disclosed. The methods include a first step of performing a cleaning process for removing a natural oxide layer formed on a semiconductor substrate and also for removing an oxide layer generated by the removal of the natural oxide layer; a second step of executing a hydrogen annealing process to form a hydrogen passivation layer and for further reducing a surface roughness of the semiconductor substrate completed in the cleaning process; a third step of forming a gate oxide layer thereon; a fourth step of performing a nitridation process on the gate oxide layer to prevent the semiconductor substrate from a permeation of ions during a subsequent gate electrode formation step; and, a fifth step of performing a subsequent thermal process to stabilize a surface of the gate oxide layer, thereby improving a defect rate of the device caused in forming the gate oxide layer.

摘要翻译： 公开了制备其上形成有栅氧化层的改进的半导体衬底的方法，以及这些衬底在制造改进的半导体器件中的用途。 所述方法包括进行用于去除形成在半导体衬底上的自然氧化物层的清洁工艺以及去除通过除去天然氧化物层而产生的氧化物层的第一步骤; 执行氢退火处理以形成氢钝化层并进一步降低在清洁过程中完成的半导体衬底的表面粗糙度的第二步骤; 在其上形成栅氧化层的第三步骤; 在栅极氧化层上进行氮化处理以防止半导体衬底在随后的栅电极形成步骤期间渗透离子的第四步骤; 以及进行后续热处理以稳定栅极氧化物层的表面的第五步骤，从而提高在形成栅极氧化物层时引起的器件的缺陷率。