公开(公告)号：US20240333173A1

公开(公告)日：2024-10-03

申请号：US18623734

申请日：2024-04-01

Applicant: Inertech IP LLC

Inventor： Subrata K Mondal

IPC: H02M7/487 ,  H02J9/06 ,  H02M1/084 ,  H02M3/04 ,  H02M7/483 ,  H02M7/49 ,  H02M7/5387

CPC classification number: H02M7/487 ,  H02J9/061 ,  H02M3/04 ,  H02M1/0845 ,  H02M7/4835 ,  H02M7/49 ,  H02M7/53873 ,  H02M7/53875 ,  H02M7/53876

Abstract: Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

公开(公告)号：US09912251B2

公开(公告)日：2018-03-06

申请号：US15493978

申请日：2017-04-21

Applicant: Inertech IP LLC

Inventor： Subrata K Mondal

IPC: H02J3/12 ,  G05F1/00 ,  H02M7/487 ,  H02J9/06 ,  H02M3/04

CPC classification number: H02M7/487 ,  H02J9/061 ,  H02M3/04 ,  H02M2007/53876

Abstract: Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

公开(公告)号：US11949343B2

公开(公告)日：2024-04-02

申请号：US17130779

申请日：2020-12-22

Applicant: Inertech IP LLC

Inventor： Subrata K Mondal

IPC: H02M7/487 ,  H02J9/06 ,  H02M3/04 ,  H02M7/5387 ,  H02M1/084 ,  H02M7/483 ,  H02M7/49

CPC classification number: H02M7/487 ,  H02J9/061 ,  H02M3/04 ,  H02M1/0845 ,  H02M7/4835 ,  H02M7/49 ,  H02M7/53873 ,  H02M7/53875 ,  H02M7/53876

Abstract: Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle Θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

公开(公告)号：US20170229977A1

公开(公告)日：2017-08-10

申请号：US15493978

申请日：2017-04-21

Applicant: Inertech IP LLC

Inventor： Subrata K Mondal

IPC: H02M7/487 ,  H02M3/04 ,  H02J9/06

CPC classification number: H02M7/487 ,  H02J9/061 ,  H02M3/04 ,  H02M2007/53876

Abstract: Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.