公开(公告)号：US20250079275A1

公开(公告)日：2025-03-06

申请号：US18781582

申请日：2024-07-23

Applicant: Infineon Technologies AG

Inventor： Wolfgang SCHOLZ ,  Marcus BÖHM ,  Bernd Richard SCHMÖLZER ,  Andre Rainer STEGNER ,  Lisa Marie HOLZMANN ,  Thorsten SCHARF

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/07

Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

公开(公告)号：US20200098869A1

公开(公告)日：2020-03-26

申请号：US16576042

申请日：2019-09-19

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim SCHULZE ,  Thomas BASLER ,  Andre Rainer STEGNER

IPC: H01L29/167 ,  H01L29/16

Abstract: A silicon carbide device includes a transistor cell with a front side doping region, a body region, and a drift region. The body region includes a first portion having a first average net doping concentration and a second portion having a second average net doping concentration. The first portion and the second portion have an extension of at least 50 nm in a vertical direction. The first average net doping concentration is at least two times the second average net doping concentration, and the first average net doping concentration is at least 1·1017 cm−3.

公开(公告)号：US20170179224A1

公开(公告)日：2017-06-22

申请号：US15386077

申请日：2016-12-21

Applicant: Infineon Technologies AG

Inventor： Andreas HAERTL ,  Martin BRANDT ,  Andre Rainer STEGNER ,  Martin STUTZMANN

IPC: H01L29/06

Abstract: A power semiconductor device includes a semiconductor substrate including at least one electrical structure. The at least one electrical structure has a blocking voltage of more than 20V. Further, the power semiconductor device includes an electrically insulating layer structure formed over at least a portion of a lateral surface of the semiconductor substrate. The electrically insulating layer structure embeds one or more local regions for storing charge carriers. Further, the one or more local regions includes in at least one direction a dimension of less than 200 nm.