公开(公告)号：US20250079275A1

公开(公告)日：2025-03-06

申请号：US18781582

申请日：2024-07-23

Applicant: Infineon Technologies AG

Inventor： Wolfgang SCHOLZ ,  Marcus BÖHM ,  Bernd Richard SCHMÖLZER ,  Andre Rainer STEGNER ,  Lisa Marie HOLZMANN ,  Thorsten SCHARF

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L25/07

Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

公开(公告)号：US20240105678A1

公开(公告)日：2024-03-28

申请号：US18243231

申请日：2023-09-07

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Angela KESSLER ,  Thorsten SCHARF

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/19 ,  H01L24/24 ,  H01L25/50 ,  H01L2224/19 ,  H01L2224/24137

Abstract: A chip package is provided. The chip package includes an electrically conductive carrier structure, a first power chip on the carrier structure having a control contact pad and a second power chip on the carrier structure having a control contact pad. The first and second power chips are arranged with their respective control contact pad facing a redistribution layer. A logic chip is arranged with a logic contact pad facing a redistribution layer, wherein the redistribution layer connects the logic contact pad with the respective control pads of the power chips.

公开(公告)号：US20220238481A1

公开(公告)日：2022-07-28

申请号：US17722929

申请日：2022-04-18

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Thorsten SCHARF ,  Ralf WOMBACHER

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/055 ,  H01L23/48 ,  H01L21/48

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

公开(公告)号：US20220157774A1

公开(公告)日：2022-05-19

申请号：US17502163

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Martin GRUBER ,  Thorsten SCHARF

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

公开(公告)号：US20170250152A1

公开(公告)日：2017-08-31

申请号：US15436778

申请日：2017-02-18

Applicant: Infineon Technologies AG

Inventor： Thorsten SCHARF ,  Steffen Jordan ,  Wolfgang Schober ,  Thomas Ziegler

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L24/43 ,  H01L24/45 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/18 ,  H01L2924/01015

Abstract: A package comprising an electronic chip, a laminate-type encapsulant at least partially encapsulating the electronic chip, a wiring structure extending from the electronic chip up to a contact pad, and a completely galvanically formed solderable exterior electric contact electrically coupled with the electronic chip by being arranged on the contact pad.

公开(公告)号：US20240347369A1

公开(公告)日：2024-10-17

申请号：US18605019

申请日：2024-03-14

Applicant: Infineon Technologies AG

Inventor： Frank SINGER ,  Thorsten SCHARF ,  Evelyn NAPETSCHNIG

IPC: H01L21/683 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L21/6836 ,  H01L21/568 ,  H01L21/60 ,  H01L2021/6006 ,  H01L2221/68318 ,  H01L2221/68354

Abstract: A method is disclosed. In one example, the method comprises mounting an electronic component on an adhesive base structure on a temporary carrier, and dissolving at least part of the base structure by irradiating the base structure with electromagnetic radiation to thereby release the electronic component.

公开(公告)号：US20170278762A1

公开(公告)日：2017-09-28

申请号：US15468045

申请日：2017-03-23

Applicant: Infineon Technologies AG

Inventor： Angela KESSLER ,  Oliver HAEBERLEN ,  Matteo-Alessandro KUTSCHAK ,  Ralf OTREMBA ,  Petteri PALM ,  Boris PLIKAT ,  Thorsten SCHARF ,  Klaus SCHIESS ,  Fabian SCHNOY ,  Erich SYRI

IPC: H01L21/66 ,  H01L23/498 ,  G01N21/84 ,  H01L23/31

CPC classification number: H01L22/32 ,  G01N21/84 ,  G01N21/95684 ,  G01N2201/12 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/052 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1033

Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.

公开(公告)号：US20150221569A1

公开(公告)日：2015-08-06

申请号：US14613446

申请日：2015-02-04

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Thorsten SCHARF ,  Ralf WOMBACHER

IPC: H01L23/055 ,  H01L23/48 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L24/82 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/055 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/8285 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/82 ,  H01L2224/83

Abstract: Electronic module (100), which comprises a first substrate (102), a first dielectric layer (104) on the first substrate (102), at least one electronic chip (106), which is mounted with a first main surface (108) directly or indirectly on partial region of the first dielectric layer (104), a second substrate (110) over a second main surface (114) of the at least one electronic chip (106), and an electrical contacting (116) for the electric contact of the at least one electronic chip (106) through the first dielectric layer (104), wherein the first adhesion layer (104) on the first substrate (102) extends over an area, which exceeds the first main surface (108).

Abstract translation: 电子模块（100），其包括第一基板（102），第一基板（102）上的第一介电层（104），至少一个电子芯片（106），其安装有第一主表面（108） 直接或间接地在第一介电层（104）的部分区域上，在所述至少一个电子芯片（106）的第二主表面（114）上方的第二基板（110）以及用于电气 所述至少一个电子芯片（106）通过所述第一介电层（104）的接触，其中所述第一基板（102）上的所述第一粘合层（104）延伸超过所述第一主表面（108）的区域。

公开(公告)号：US20150115475A1

公开(公告)日：2015-04-30

申请号：US14069361

申请日：2013-10-31

Applicant: Infineon Technologies AG

Inventor： Petteri PALM ,  Thorsten SCHARF

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83192 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract translation: 一种器件包括包括第一面的第一半导体芯片，其中第一接触焊盘布置在第一面上。 该器件还包括第二半导体芯片，其包括第一面，其中第一接触焊盘布置在第一面上，其中第一半导体芯片和第二半导体芯片布置成使得第一半导体芯片的第一面朝向 第一方向和第二半导体芯片的第一面朝向与第一方向相反的第二方向。 第一半导体芯片位于第二半导体芯片的外形的横向外侧。