公开(公告)号：US20230197586A1

公开(公告)日：2023-06-22

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/211

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US12278171B2

公开(公告)日：2025-04-15

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US20230197585A1

公开(公告)日：2023-06-22

申请号：US17556341

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow ,  Khay Chwan Andrew Saw ,  Fee Hoon Wendy Wong

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L2224/211

Abstract: A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.