公开(公告)号：US11469161B2

公开(公告)日：2022-10-11

申请号：US17004070

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Chan Lam Cha ,  Wolfgang Hetzel ,  Swee Kah Lee ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

公开(公告)号：US20220068773A1

公开(公告)日：2022-03-03

申请号：US17004070

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Chan Lam Cha ,  Wolfgang Hetzel ,  Swee Kah Lee ,  Stefan Macheiner

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

公开(公告)号：US12278171B2

公开(公告)日：2025-04-15

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US20230197585A1

公开(公告)日：2023-06-22

申请号：US17556341

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow ,  Khay Chwan Andrew Saw ,  Fee Hoon Wendy Wong

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L2224/211

Abstract: A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.

公开(公告)号：US10396018B2

公开(公告)日：2019-08-27

申请号：US15822745

申请日：2017-11-27

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Chan Lam Cha ,  Wei Han Koo ,  Andreas Kucher ,  Theng Chao Long

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/495 ,  H03K17/687 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H02M1/088 ,  H02P27/04

Abstract: A semiconductor package includes a plurality of half bridge assemblies each including a metal lead, a first power transistor die attached to a first side of the metal lead, and a second power transistor die disposed under the first power transistor die and attached to a second side of the metal lead opposite the first side. Each metal lead has a notch which exposes one or more bond pads at a side of the second power transistor die attached to the metal lead. The semiconductor package also includes a controller die configured to control the power transistor dies. Each power transistor die, each metal lead and the controller die are embedded in a mold compound. Bond wire connections are provided between the controller die and the one or more bond pads at the side of each second power transistor die exposed by the notch in the corresponding metal lead.

公开(公告)号：US20230170329A1

公开(公告)日：2023-06-01

申请号：US17888669

申请日：2022-08-16

Applicant: Infineon Technologies AG

Inventor： Sock Chien Tey ,  Keck Tim Ang ,  Chan Lam Cha ,  Chau Fatt Chiang ,  Badrul Hisyam Ismail ,  Desmond Jenn Yong Loo ,  Ronizan Mohd Salleh ,  Norliza Morban ,  Si Hao Vincent Yeo ,  Chee Mun Wai ,  Fee Hoon Wendy Wong

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/4824 ,  H01L24/16 ,  H01L23/5386 ,  H01L24/32 ,  H01L21/568 ,  H01L25/50 ,  H01L2224/16157 ,  H01L2224/32145

Abstract: A method of forming a semiconductor package includes providing a metal baseplate including a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US20220199478A1

公开(公告)日：2022-06-23

申请号：US17552914

申请日：2021-12-16

Applicant: Infineon Technologies AG

Inventor： Si Hao Vincent Yeo ,  Chan Lam Cha ,  Ying Dieh Cheong ,  Chau Fatt Chiang ,  Cher Hau Danny Koh ,  Wern Ken Daryl Wee ,  Swee Kah Lee ,  Desmond Jenn Yong Loo ,  Fortunato Lopez ,  Norliza Morban ,  Khay Chwan Andrew Saw ,  Sock Chien Tey ,  Mei Yong Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

公开(公告)号：US11274984B2

公开(公告)日：2022-03-15

申请号：US16890461

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Paul Armand Asentista Calo ,  Chan Lam Cha ,  Kok Yau Chua ,  Jo Ean Chye ,  Chee Hong Lee ,  Swee Kah Lee ,  Theng Chao Long ,  Jayaganasan Narayanasamy ,  Khay Chwan Saw

IPC: G01L9/00 ,  G01L19/14

Abstract: A pressure sensor includes a lidless structure defining an internal chamber for a sealed environment and presenting an aperture; a chip including a membrane deformable on the basis of external pressure, the chip being mounted outside the lidless structure in correspondence to the aperture so that the membrane closes the sealed environment; and a circuitry configured to provide a pressure measurement information based on the deformation of the membrane.

公开(公告)号：US20170011989A1

公开(公告)日：2017-01-12

申请号：US14792908

申请日：2015-07-07

Applicant: Infineon Technologies AG

Inventor： Chip King Tan ,  Chan Lam Cha

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/85 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/00 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A lead frame includes a die paddle, a first lead, and a U-notch coupling the die paddle to the first lead. The U-notch extends from the die paddle and the first lead. The U-notch is configured to be removed to electrically isolate the first lead from the die paddle.

Abstract translation: 引线框架包括管芯焊盘，第一引线和将管芯焊盘连接到第一引线的U形凹口。 U形凹口从模片和第一导线延伸。 U形槽被配置为被去除以将第一引线与管芯焊盘电隔离。

公开(公告)号：US12300559B2

公开(公告)日：2025-05-13

申请号：US17552914

申请日：2021-12-16

Applicant: Infineon Technologies AG

Inventor： Si Hao Vincent Yeo ,  Chan Lam Cha ,  Ying Dieh Cheong ,  Chau Fatt Chiang ,  Cher Hau Danny Koh ,  Wern Ken Daryl Wee ,  Swee Kat Lee ,  Desmond Jenn Yong Loo ,  Fortunato Lopez ,  Norliza Morban ,  Khay Chwan Andrew Saw ,  Sock Chien Tey ,  Mei Yong Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.