公开(公告)号：US20220199478A1

公开(公告)日：2022-06-23

申请号：US17552914

申请日：2021-12-16

Applicant: Infineon Technologies AG

Inventor： Si Hao Vincent Yeo ,  Chan Lam Cha ,  Ying Dieh Cheong ,  Chau Fatt Chiang ,  Cher Hau Danny Koh ,  Wern Ken Daryl Wee ,  Swee Kah Lee ,  Desmond Jenn Yong Loo ,  Fortunato Lopez ,  Norliza Morban ,  Khay Chwan Andrew Saw ,  Sock Chien Tey ,  Mei Yong Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

公开(公告)号：US10937744B2

公开(公告)日：2021-03-02

申请号：US16282506

申请日：2019-02-22

Applicant: Infineon Technologies AG

Inventor： Wern Ken Daryl Wee ,  Sock Chien Tey ,  Si Hao Vincent Yeo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.

公开(公告)号：US12278171B2

公开(公告)日：2025-04-15

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US20230197585A1

公开(公告)日：2023-06-22

申请号：US17556341

申请日：2021-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow ,  Khay Chwan Andrew Saw ,  Fee Hoon Wendy Wong

IPC: H01L23/495 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L2224/211

Abstract: A method includes providing a lead frame including a die pad and a plurality of leads, providing a first semiconductor die that includes a first load terminal disposed on a main surface, providing a second semiconductor die that includes a plurality of I/O terminals disposed on a main surface, mounting the first and second semiconductor dies on the lead frame such that the main surfaces of the first and second semiconductor dies face away from the die pad, forming an encapsulant body of mold compound that encapsulates the first and second semiconductor dies, forming a plurality of conductive tracks on an upper surface of the encapsulant body that electrically connect at least some of the I/O terminals to a first group of the leads, and forming a metal pad on the upper surface of the encapsulant body that electrically connects the first load terminal to a second lead.

公开(公告)号：US12176222B2

公开(公告)日：2024-12-24

申请号：US17536538

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Thorsten Meyer ,  Chan Lam Cha ,  Wern Ken Daryl Wee ,  Chee Hong Lee ,  Swee Kah Lee ,  Norliza Morban ,  Khay Chwan Andrew Saw

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US20230170226A1

公开(公告)日：2023-06-01

申请号：US17536538

申请日：2021-11-29

Applicant: Infineon Technologies AG

Inventor： Chau Fatt Chiang ,  Thorsten Meyer ,  Chan Lam Cha ,  Wern Ken Daryl Wee ,  Chee Hong Lee ,  Swee Kah Lee ,  Norliza Morban ,  Khay Chwan Andrew Saw

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L21/4853 ,  H01L23/31 ,  H01L23/49811 ,  H01L23/367 ,  H01L21/568 ,  H01L25/50 ,  H01L25/18

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

公开(公告)号：US12300559B2

公开(公告)日：2025-05-13

申请号：US17552914

申请日：2021-12-16

Applicant: Infineon Technologies AG

Inventor： Si Hao Vincent Yeo ,  Chan Lam Cha ,  Ying Dieh Cheong ,  Chau Fatt Chiang ,  Cher Hau Danny Koh ,  Wern Ken Daryl Wee ,  Swee Kat Lee ,  Desmond Jenn Yong Loo ,  Fortunato Lopez ,  Norliza Morban ,  Khay Chwan Andrew Saw ,  Sock Chien Tey ,  Mei Yong Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495

Abstract: A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

公开(公告)号：US20230197586A1

公开(公告)日：2023-06-22

申请号：US18084604

申请日：2022-12-20

Applicant: Infineon Technologies AG

Inventor： Chan Lam Cha ,  Wern Ken Daryl Wee ,  Hoe Jian Chong ,  Chin Kee Leow

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L24/20 ,  H01L24/19 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/211

Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.

公开(公告)号：US20200273813A1

公开(公告)日：2020-08-27

申请号：US16282506

申请日：2019-02-22

Applicant: Infineon Technologies AG

Inventor： Wern Ken Daryl Wee ,  Sock Chien Tey ,  Si Hao Vincent Yeo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a substrate, a semiconductor die, dendrite, and a mold material. The substrate includes a die pad. The die pad includes roughening features. The semiconductor die is attached to the die pad such that the roughening features are adjacent to the semiconductor die. The dendrite is on the roughening features adjacent to the semiconductor die. The mold material encapsulates the semiconductor die, the dendrite, and at least a portion of the substrate.