公开(公告)号：US20200227518A1

公开(公告)日：2020-07-16

申请号：US16828665

申请日：2020-03-24

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L21/22 ,  H01L29/78 ,  H01L21/223 ,  H01L21/311 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a plurality of first and second stripe-shaped cell trench structures formed in a semiconductor substrate and extending lengthwise in parallel with one another. Each stripe-shaped cell trench structure includes a buried electrode and an insulator layer between the buried electrode and the semiconductor substrate. A recess is formed in the insulator layer along a sidewall of one or more of the first stripe-shaped cell trench structures and vertically extends to a corresponding heavily doped contact zone. An electrically conductive material disposed in each recess contacts the corresponding buried electrode, a corresponding source zone and a corresponding heavily doped contact zone at the sidewall. Two or more of the first stripe-shaped cell trench structures are interposed between neighboring ones of the second stripe-shaped cell trench structures. Source zones alternate with portions of body zones in a lateral direction parallel to the stripe-shaped cell trench structures.

公开(公告)号：US20170243969A1

公开(公告)日：2017-08-24

申请号：US15589531

申请日：2017-05-08

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

公开(公告)号：US20150041962A1

公开(公告)日：2015-02-12

申请号：US13963312

申请日：2013-08-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

Abstract translation: 第一和第二单元沟槽结构从第一表面延伸到半导体衬底。 第一单元沟槽结构包括第一掩埋电极和第一绝缘体层之间的第一掩埋电极和分隔第一和第二单元沟道结构的半导体台面之间的第一绝缘体层。 覆盖层覆盖第一表面。 将覆盖层图案化以形成具有大于第一绝缘体层的厚度的最小宽度的开口。 开口在第一表面暴露第一绝缘体层的第一垂直截面。 去除第一绝缘体层的暴露部分以在半导体台面和第一掩埋电极之间形成凹部。 接触结构位于开口和凹部中。 接触结构电连接半导体台面中的掩埋区和第一掩埋电极，并允许较窄的半导体台面宽度。

公开(公告)号：US20180366541A1

公开(公告)日：2018-12-20

申请号：US16110508

申请日：2018-08-23

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L21/311 ,  H01L21/265 ,  H01L21/223

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

公开(公告)号：US09666663B2

公开(公告)日：2017-05-30

申请号：US13963312

申请日：2013-08-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.