公开(公告)号：US20240304538A1

公开(公告)日：2024-09-12

申请号：US18591580

申请日：2024-02-29

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer ,  Matthias Bürger ,  Ulrich Nolten ,  Mark Essert

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49844 ,  H01L23/14 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/181

Abstract: A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.