公开(公告)号：US20240304538A1

公开(公告)日：2024-09-12

申请号：US18591580

申请日：2024-02-29

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer ,  Matthias Bürger ,  Ulrich Nolten ,  Mark Essert

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49844 ,  H01L23/14 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/181

Abstract: A power semiconductor module arrangement includes: a substrate having a dielectric insulation layer and a first metallization layer arranged on a first surface of the dielectric insulation layer; at least one semiconductor body arranged on and attached to the first metallization layer by an electrically conductive connection layer; and at least one electrically conducting element arranged on the first metallization layer. The first metallization layer is a structured layer having a plurality of different sub-sections. The first metallization layer has a uniform thickness in a vertical direction, the vertical direction being perpendicular to the first surface of the dielectric insulation layer. Each electrically conducting element is arranged on and covers a subarea of a sub-section, thereby increasing a cross-sectional area of the subarea of the respective sub-section. Each electrically conducting element includes an electrically conductive connection layer without a semiconductor body arranged thereon.

公开(公告)号：US20240162129A1

公开(公告)日：2024-05-16

申请号：US18504309

申请日：2023-11-08

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer ,  Michael Fügl ,  Frank Singer ,  Thorsten Meyer ,  Fabian Craes ,  Andreas Grassmann ,  Frederik Otto

IPC: H01L23/498 ,  B82Y10/00 ,  H01L23/00 ,  H01L23/31 ,  H01L25/07

CPC classification number: H01L23/49811 ,  B82Y10/00 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49844 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181

Abstract: A substrate arrangement includes: a first metallization layer, nanowires arranged on a surface of the first metallization layer; and a component arranged on the first metallization layer such that a first subset of the nanowires is arranged between the first metallization layer and the component. The nanowires are evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer. Each nanowire includes first and second ends. The first end of each nanowire is inseparably connected to the surface of the first metallization layer. The second end of each nanowire of the first subset is inseparably connected to a surface of one of the component such that the first subset of nanowires forms a permanent connection between the first metallization layer and the component. There are fewer nanowires in the first subset of nanowires than there are total nanowires.

公开(公告)号：US20230360984A1

公开(公告)日：2023-11-09

申请号：US18142106

申请日：2023-05-02

Applicant: Infineon Technologies AG

Inventor： Christoph Bayer

IPC: H01L23/31 ,  H01L23/16 ,  H01L23/00 ,  H01L23/04

CPC classification number: H01L23/16 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/562

Abstract: A semiconductor package including a die carrier, at least one semiconductor die disposed on the die carrier, a potting compound at least partially covering the die carrier and the semiconductor die, and at least one structure that is configured to withstand a change of the volume of the potting compound occurring under changed external conditions in a targeted manner.