公开(公告)号：US20180308827A1

公开(公告)日：2018-10-25

申请号：US15957561

申请日：2018-04-19

Applicant: Infineon Technologies AG

Inventor： Matthias Wissen ,  Daniel Domes ,  Andreas Groove

IPC: H01L25/10 ,  H01L23/492 ,  H01L23/52 ,  H01L23/367

CPC classification number: H01L25/105 ,  H01L23/3675 ,  H01L23/4922 ,  H01L23/52 ,  H01L25/115 ,  H01L25/117 ,  H05K1/0216

Abstract: A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.