公开(公告)号：US20040252576A1

公开(公告)日：2004-12-16

申请号：US10805670

申请日：2004-03-19

Applicant: Infineon Technologies AG

Inventor： Franz Hofmann ,  Richard Johannes Luyken ,  Michael Specht

IPC: G11C008/02

CPC classification number: H01L27/11517 ,  H01L27/115

Abstract: Method for fabricating a semiconductor memory element arrangement. A layer system, including a floating gate and a tunnel barrier arrangement formed on the floating gate, is formed on an electrically insulating layer. A first trench structure is formed in the layer system, and the first trench structure has first parallel trenches extending as far as the insulating layer. A second trench structure is formed in the layer system, and has second parallel trenches arranged perpendicular to the first trenches and extending as far as the insulating layer. First and second gate electrodes are formed in the first and second trench structures. The first gate electrode is adjacent to the floating gate through which first gate electrode electrical charge can be fed or can be dissipated from. The second gate electrode is adjacent to the tunnel barrier arrangement, and can control an electrical charge transmission of the tunnel barrier arrangement.

Abstract translation: 半导体存储元件布置的制造方法。 在电绝缘层上形成包括形成在浮动栅极上的浮动栅极和隧道势垒装置的层系统。 在层系统中形成第一沟槽结构，并且第一沟槽结构具有延伸至绝缘层的第一平行沟槽。 在层系统中形成第二沟槽结构，并且具有垂直于第一沟槽布置并延伸至绝缘层的第二平行沟槽。 第一和第二栅电极形成在第一和第二沟槽结构中。 第一栅电极与浮置栅极相邻，第一栅电极电荷可以通过该栅极馈送或可从其中消散。 第二栅电极与隧道势垒装置相邻，并且可以控制隧道势垒装置的电荷传输。

公开(公告)号：US20040266088A1

公开(公告)日：2004-12-30

申请号：US10839800

申请日：2004-05-06

Applicant: Infineon Technologies AG

Inventor： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rosner ,  Till Schlosser ,  Michael Specht

IPC: H01L021/8238

CPC classification number: H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.