公开(公告)号：US11616509B1

公开(公告)日：2023-03-28

申请号：US17534646

申请日：2021-11-24

Applicant: Infineon Technologies AG

Inventor： Francesco Lombardo ,  Dmytro Cherniak ,  Luigi Grimaldi ,  Nicolo Guarducci

IPC: H03M1/06

Abstract: A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.

公开(公告)号：US12249998B2

公开(公告)日：2025-03-11

申请号：US17903238

申请日：2022-09-06

Applicant: Infineon Technologies AG

Inventor： Andreas Schwarz ,  Thomas Bauernfeind ,  Thorsten Brandt ,  Bernhard Greslehner-Nimmervoll ,  Daniel Maier ,  Francesco Lombardo ,  Nicolo Guarducci

IPC: H03L7/099 ,  G01S13/34 ,  H03L7/091

Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.

公开(公告)号：US20240080032A1

公开(公告)日：2024-03-07

申请号：US17903238

申请日：2022-09-06

Applicant: Infineon Technologies AG

Inventor： Andreas Schwarz ,  Thomas Bauernfeind ,  Thorsten Brandt ,  Bernhard Greslehner-Nimmervoll ,  Daniel Maier ,  Francesco Lombardo ,  Nicolo Guarducci

IPC: H03L7/099 ,  G01S13/34 ,  H03L7/091

CPC classification number: H03L7/0992 ,  G01S13/343 ,  H03L7/091

Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.

公开(公告)号：US20240077579A1

公开(公告)日：2024-03-07

申请号：US18066029

申请日：2022-12-14

Applicant: Infineon Technologies AG

Inventor： Thomas Bauernfeind ,  Andreas Schwarz ,  Nicolo Guarducci ,  Thorsten Brandt ,  Francesco Lombardo ,  Bernhard Greslehner-Nimmervoll ,  Daniel Maier

IPC: G01S7/35

CPC classification number: G01S7/352

Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.