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Patent Agency Ranking
公开(公告)号：US12294638B2
公开(公告)日：2025-05-06
申请号：US18359065
申请日：2023-07-26
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Thomas Josef Bauernfeind , Stefan Schmalzl , Thomas Obermueller , Martin Louda , Furqan Farooq Fazili
Abstract: A method for monitoring an RF receiver includes generating of a digital test signal based on a signal, wherein the digital test signal includes a stream of digital test samples having a digital test sample; generating a monitoring signal based on the digital test signal; and coupling of the monitoring signal into a receiver path. The monitoring signal is processed in the receiver path to generate a processed monitoring signal and a stream of digital monitoring samples representing the processed monitoring signal. Information is determined indicating at least one property related to the receiver path based on a processing of a set of digital monitoring samples of the stream of digital monitoring samples. The set of digital monitoring samples includes a digital monitoring sample. The method further includes controlling the RF receiver such that the digital monitoring sample is generated a predetermined time duration after generating the digital test sample.
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公开(公告)号：US11418205B1
公开(公告)日：2022-08-16
申请号：US17208761
申请日：2021-03-22
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Dmytro Cherniak , Luigi Grimaldi
Abstract: In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.
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公开(公告)号：US20240080032A1
公开(公告)日：2024-03-07
申请号：US17903238
申请日：2022-09-06
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Thomas Bauernfeind , Thorsten Brandt , Bernhard Greslehner-Nimmervoll , Daniel Maier , Francesco Lombardo , Nicolo Guarducci
CPC classification number: H03L7/0992 , G01S13/343 , H03L7/091
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
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公开(公告)号：US20240077579A1
公开(公告)日：2024-03-07
申请号：US18066029
申请日：2022-12-14
Applicant: Infineon Technologies AG
Inventor： Thomas Bauernfeind , Andreas Schwarz , Nicolo Guarducci , Thorsten Brandt , Francesco Lombardo , Bernhard Greslehner-Nimmervoll , Daniel Maier
IPC: G01S7/35
CPC classification number: G01S7/352
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.
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公开(公告)号：US12249998B2
公开(公告)日：2025-03-11
申请号：US17903238
申请日：2022-09-06
Applicant: Infineon Technologies AG
Inventor： Andreas Schwarz , Thomas Bauernfeind , Thorsten Brandt , Bernhard Greslehner-Nimmervoll , Daniel Maier , Francesco Lombardo , Nicolo Guarducci
Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.
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