公开(公告)号：US20240322499A1

公开(公告)日：2024-09-26

申请号：US18732874

申请日：2024-06-04

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder

IPC: H01R13/66 ,  G06F13/40

CPC classification number: H01R13/665 ,  G06F13/4081

Abstract: A circuit is disclosed having one or more circuits, a connector portion coupled to the one or more circuits, and comprising a plurality of pins. When the connector portion is coupled with a first connector in a first orientation, the one or more circuits are configured to operate in a first state, and when the connector portion is coupled with the first connector in a second orientation, at least one pin of the plurality of pins receives a signal causing the one or more circuits to operate in a second state different from the first state. The second orientation being different from the first orientation.

公开(公告)号：US20240143423A1

公开(公告)日：2024-05-02

申请号：US17979139

申请日：2022-11-02

Applicant: Infineon Technologies AG

Inventor： Patrik Eder ,  Christian Mueller

IPC: G06F11/00

CPC classification number: G06F11/004

Abstract: Techniques, described herein, include solutions for evaluating a pre-failure condition of a data link. The techniques described allow for detection of the pre-failure condition before actual failure of the data link. A device may receive a first set of training data and compare the first set of training data to a pre-determined set of training data to obtain a first set of values at a first time. The process may be repeated at a second time with a second set of training data and a second set of values respectively. First and second quality metrics may be obtained using the first and second set of values respectively. Based on the first and second quality metrics and a time interval between the first and second times, the pre-failure condition may be determined.

公开(公告)号：US20240004992A1

公开(公告)日：2024-01-04

申请号：US18345008

申请日：2023-06-30

Applicant: Infineon Technologies AG

Inventor： Patrik Eder ,  Rainer Wolfgang Kaiser

IPC: G06F21/54 ,  G06F21/55

CPC classification number: G06F21/54 ,  G06F21/554

Abstract: In an embodiment an integrated circuit comprises a plurality of ports. Of a plurality of gating circuits, each gating circuit blocks or grants access to at least one of the ports depending on a release signal. From a plurality of configuration registers, each configuration register for stores the information to which group a gating circuit of the plurality of gating circuits belongs. A tag evaluation circuit receives an identifier from an access request from a component and outputs a group identifier for the access. There is a plurality of comparison circuits. Each comparison circuit compares the group identifier with the content of one of the configuration registers and outputs the release signal to a gating circuit of the plurality of gating circuits.

公开(公告)号：US12034256B2

公开(公告)日：2024-07-09

申请号：US17329559

申请日：2021-05-25

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder

IPC: H01R13/66 ,  G06F13/40 ,  G06F13/42

CPC classification number: H01R13/665 ,  G06F13/4081

Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.

公开(公告)号：US20230267094A1

公开(公告)日：2023-08-24

申请号：US17679330

申请日：2022-02-24

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder ,  Kajetan Nuernberger

IPC: G06F15/78 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F15/7807 ,  G06F9/45558 ,  G06F9/30003 ,  G06F2009/45591

Abstract: In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.

公开(公告)号：US20210367366A1

公开(公告)日：2021-11-25

申请号：US17329559

申请日：2021-05-25

Applicant: Infineon Technologies AG

Inventor： Albrecht Mayer ,  Patrik Eder

IPC: H01R12/75 ,  H01R13/66 ,  H01R13/04

Abstract: A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.