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公开(公告)号：US10127176B2
公开(公告)日：2018-11-13
申请号：US15420646
申请日：2017-01-31
Applicant: Infineon Technologies AG
Inventor： Paul Wallner , Dieter Metzner , Martin Streibl
Abstract: In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.
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公开(公告)号：US09417983B2
公开(公告)日：2016-08-16
申请号：US13908702
申请日：2013-06-03
Applicant: Infineon Technologies AG
Inventor： Dieter Metzner , Peter Widerin , Paul Wallner , Thomas Rickes
CPC classification number: G06F11/3027 , G06F11/3062 , G06F13/4027 , G06F13/4072
Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.
Abstract translation: 描述了用于驱动总线的电路，其包括在总线终端处耦合到至少一个信号线的至少一个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到至少一个分支的电流检测单元，其被配置为检测通过至少一个分支的电流。 电路还包括耦合到电流检测单元和发送数据输入两者的过电流确定单元。 过电流确定单元被配置为基于至少一个分支处的电流和发送数据输入处的数据来确定至少一个分支处的过电流状况。
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公开(公告)号：US09172235B2
公开(公告)日：2015-10-27
申请号：US13908770
申请日：2013-06-03
Applicant: Infineon Technologies AG
Inventor： Dieter Metzner , Peter Widerin , Paul Wallner , Thomas Rickes
CPC classification number: H02H3/08 , H04L25/0272 , H04L25/0282
Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.
Abstract translation: 描述了用于驱动总线的电路，其包括在总线的终止处耦合到至少一个信号线的多个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到发射数据输入的过电流验证单元，其被配置为至少部分地基于发射数据输入端的数据来验证在多个分支的第一支路处检测到的过电流状况 。 电路还包括耦合到过电流验证单元的分支控制单元，其被配置为响应于在第一分支处的验证过电流状况来禁用多个分支中的至少一个分支。
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Patent Agency Ranking
公开(公告)号：US20140359190A1
公开(公告)日：2014-12-04
申请号：US13908702
申请日：2013-06-03
Applicant: Infineon Technologies AG
Inventor： Dieter Metzner , Peter Widerin , Paul Wallner , Thomas Rickes
CPC classification number: G06F11/3027 , G06F11/3062 , G06F13/4027 , G06F13/4072
Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.
Abstract translation: 描述了用于驱动总线的电路，其包括在总线终端处耦合到至少一个信号线的至少一个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到至少一个分支的电流检测单元，其被配置为检测通过至少一个分支的电流。 电路还包括耦合到电流检测单元和发送数据输入两者的过电流确定单元。 过电流确定单元被配置为基于至少一个分支处的电流和发送数据输入处的数据来确定至少一个分支处的过电流状况。
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公开(公告)号：US20170139870A1
公开(公告)日：2017-05-18
申请号：US15420646
申请日：2017-01-31
Applicant: Infineon Technologies AG
Inventor： Paul Wallner , Dieter Metzner , Martin Streibl
CPC classification number: G06F13/4072 , G06F13/124 , G06F13/4063 , G06F13/4286 , G06F13/4295 , Y02D10/14 , Y02D10/151
Abstract: In accordance with an embodiment, a receiver includes a receiving unit configured to receive a first received bus signal and a second received bus signal based on a bus input signal. The receiver also includes a first state machine configured to determine that a first output signal is a first symbol in response to the first received bus signal transitioning from a first bus state to a second bus state and staying in the second bus state for less than a first predetermined period of time, and a second symbol in response to the first received bus signal transitioning from the first bus state to the second bus state and staying in the second bus state for at least the first predetermined period of time. Additionally, the receiver includes a second state machine.
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公开(公告)号：US09582451B2
公开(公告)日：2017-02-28
申请号：US13756835
申请日：2013-02-01
Applicant: Infineon Technologies AG
Inventor： Paul Wallner , Dieter Metzner , Martin Streibl
CPC classification number: G06F13/4072 , G06F13/124 , G06F13/4063 , G06F13/4286 , G06F13/4295 , Y02D10/14 , Y02D10/151
Abstract: In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.
Abstract translation: 根据实施例，接收机包括被配置为耦合到总线的第一状态机。 第一状态机被配置为如果第一接收总线信号从第一总线状态转换到第二总线状态并且在第二总线状态下停留小于第一预定时间段，则第一输出信号被确定为第一符号 并且如果第一接收总线信号从第一总线状态转变到第二总线状态并且在至少第一预定时间段内保持在第二总线状态，则第一输出信号是第二符号。
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公开(公告)号：US20140355158A1
公开(公告)日：2014-12-04
申请号：US13908770
申请日：2013-06-03
Applicant: Infineon Technologies AG
Inventor： Dieter Metzner , Peter Widerin , Paul Wallner , Thomas Rickes
IPC: H02H3/08
CPC classification number: H02H3/08 , H04L25/0272 , H04L25/0282
Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.
Abstract translation: 描述了用于驱动总线的电路，其包括在总线的终止处耦合到至少一个信号线的多个分支和被配置为接收电路驱动通过总线的数据的发送数据输入。 电路还包括耦合到发射数据输入的过电流验证单元，其被配置为至少部分地基于发射数据输入端的数据来验证在多个分支的第一支路处检测到的过电流状况 。 电路还包括耦合到过电流验证单元的分支控制单元，其被配置为响应于在第一分支处的验证过电流状况来禁用多个分支中的至少一个分支。
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公开(公告)号：US20140223050A1
公开(公告)日：2014-08-07
申请号：US13756835
申请日：2013-02-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Paul Wallner , Dieter Metzner , Martin Streibl
IPC: G06F13/40
CPC classification number: G06F13/4072 , G06F13/124 , G06F13/4063 , G06F13/4286 , G06F13/4295 , Y02D10/14 , Y02D10/151
Abstract: In accordance with an embodiment, a receiver includes a first state machine configured to be coupled to a bus. The first state machine is configured to determine that a first output signal is a first symbol if a first received bus signal transitions from a first bus state to a second bus state and stays in the second bus state for less than a first predetermined period of time, and the first output signal is a second symbol if the first received bus signal transitions from the first bus state to the second bus state and stays in the second bus state for at least the first predetermined period of time.
Abstract translation: 根据实施例，接收机包括被配置为耦合到总线的第一状态机。 第一状态机被配置为如果第一接收总线信号从第一总线状态转换到第二总线状态并且在第二总线状态下停留小于第一预定时间段，则第一输出信号被确定为第一符号 并且如果第一接收总线信号从第一总线状态转变到第二总线状态并且在至少第一预定时间段内保持在第二总线状态，则第一输出信号是第二符号。
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