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公开(公告)号：US20230267999A1
公开(公告)日：2023-08-24
申请号：US18171426
申请日：2023-02-20
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Sebastian Kiesel
CPC classification number: G11C13/0064 , G11C13/004 , G11C13/0069 , G11C29/38
Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.
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公开(公告)号：US20220406375A1
公开(公告)日：2022-12-22
申请号：US17844785
申请日：2022-06-21
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Sebastian Kiesel
Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.
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公开(公告)号：US12073880B2
公开(公告)日：2024-08-27
申请号：US17844785
申请日：2022-06-21
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Sebastian Kiesel
CPC classification number: G11C13/004 , G11C7/08 , G11C7/1039 , G11C13/0026 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C2013/0054
Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.
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