公开(公告)号：US12147303B2

公开(公告)日：2024-11-19

申请号：US18159365

申请日：2023-01-25

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Alexander Klockmann ,  Thomas Rabenalt

IPC: G06F11/10

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

公开(公告)号：US20230267999A1

公开(公告)日：2023-08-24

申请号：US18171426

申请日：2023-02-20

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Sebastian Kiesel

IPC: G11C13/00 ,  G11C29/38

CPC classification number: G11C13/0064 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/38

Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.

公开(公告)号：US20220406375A1

公开(公告)日：2022-12-22

申请号：US17844785

申请日：2022-06-21

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Sebastian Kiesel

IPC: G11C13/00 ,  G11C7/08 ,  G11C7/10

Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.

公开(公告)号：US20220345157A1

公开(公告)日：2022-10-27

申请号：US17719648

申请日：2022-04-13

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Alexander Klockmann ,  Thomas Rabenalt

IPC: H03M13/15

Abstract: A solution for detecting a multibyte error in a code word of a shortened error code is proposed, the shortened error code is a τ-byte-correcting error code, wherein bytes of the code word of the shortened error code determined a first range, the non-correctable multibyte error is detected if at least one of the following conditions is met: (a) at least one error position signal does not lie in the first range; (b) at least one error position signal indicates at least one error but fewer than terrors in the first range and no 1-byte error to (τ−1)-byte error is present.

公开(公告)号：US20220231704A1

公开(公告)日：2022-07-21

申请号：US17579721

申请日：2022-01-20

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Thomas Rabenalt

IPC: H03M13/15

Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

公开(公告)号：US11314642B2

公开(公告)日：2022-04-26

申请号：US16058620

申请日：2018-08-08

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Robert Allinger ,  Robert Strenz

IPC: G06F12/02 ,  G06F12/0804 ,  G06F3/06 ,  G11C11/56 ,  G11C16/16

Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.

公开(公告)号：US20190312601A1

公开(公告)日：2019-10-10

申请号：US16380089

申请日：2019-04-10

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Thomas Rabenalt

IPC: H03M13/29 ,  H03M13/25 ,  H03M13/27 ,  G06F11/10

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

公开(公告)号：US20190057031A1

公开(公告)日：2019-02-21

申请号：US16058620

申请日：2018-08-08

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Robert Allinger ,  Robert Strenz

IPC: G06F12/0804 ,  G06F12/02 ,  G06F3/06 ,  G11C11/56 ,  G11C16/16

Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.

公开(公告)号：US10157095B2

公开(公告)日：2018-12-18

申请号：US15490950

申请日：2017-04-19

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Michael Gössel ,  Thomas Rabenalt ,  Thomas Kern

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  H03M13/29 ,  H03M13/13 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

公开(公告)号：US10133626B2

公开(公告)日：2018-11-20

申请号：US15232323

申请日：2016-08-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C17/14 ,  G11C29/04 ,  G11C29/44

Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.