公开(公告)号：US20200273778A1

公开(公告)日：2020-08-27

申请号：US16795931

申请日：2020-02-20

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Tino Karczewski ,  Michael Scheffer ,  Christian Schweikert

IPC: H01L23/473 ,  H01L25/07 ,  H01L21/48 ,  H01L25/00

Abstract: A power semiconductor arrangement includes first and second power semiconductor modules. Each power semiconductor module has a first main side and an opposing second main side. The power semiconductor modules are arranged such that a main side of the first power semiconductor module and a main side of the second power semiconductor module are facing each other. The power semiconductor arrangement further includes a cooler housing configured for direct liquid cooling of the power semiconductor modules. The cooler housing includes a fluid channel. At least one main side of the first power semiconductor module forms a sidewall of the fluid channel. A flow direction in the fluid channel along the first main side and a flow direction along the second main side of the first power semiconductor module are oriented in opposite directions.

公开(公告)号：US11004764B2

公开(公告)日：2021-05-11

申请号：US16519802

申请日：2019-07-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Tao Hong ,  Tino Karczewski ,  Matthias Lassmann ,  Christian Schweikert

IPC: H01L21/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/492 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/433

Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.

公开(公告)号：US20230178460A1

公开(公告)日：2023-06-08

申请号：US17540673

申请日：2021-12-02

Applicant: Infineon Technologies AG

Inventor： Ajay Poonjal Pai ,  Tino Karczewski ,  Adrian Lis

IPC: H01L23/495 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49555 ,  H01L25/072 ,  H01L25/18 ,  H01L23/49517 ,  H01L23/3121

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

公开(公告)号：US12113000B2

公开(公告)日：2024-10-08

申请号：US17540673

申请日：2021-12-02

Applicant: Infineon Technologies AG

Inventor： Ajay Poonjal Pai ,  Tino Karczewski ,  Adrian Lis

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/49555 ,  H01L23/49517 ,  H01L25/072 ,  H01L25/18 ,  H01L23/3121

Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

公开(公告)号：US20200035579A1

公开(公告)日：2020-01-30

申请号：US16519802

申请日：2019-07-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Tao Hong ,  Tino Karczewski ,  Matthias Lassmann ,  Christian Schweikert

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/373 ,  H01L23/495 ,  H01L23/433 ,  H01L29/16 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52

Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.