公开(公告)号：US20230253291A1

公开(公告)日：2023-08-10

申请号：US18101608

申请日：2023-01-26

Applicant: Infineon Technologies AG

Inventor： Matthias Lassmann ,  Andre Arens ,  Marco Ludwig ,  Guido Bönig

IPC: H01L23/42 ,  H01L23/373 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L21/56

CPC classification number: H01L23/42 ,  H01L23/3737 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/315 ,  H01L25/072 ,  H01L23/49833 ,  H01L23/49844 ,  H01L21/56 ,  H01L2924/182 ,  H01L2924/13055 ,  H01L2224/32225 ,  H01L24/48

Abstract: A power semiconductor module arrangement includes a housing, a substrate arranged inside the housing, a printed circuit board arranged inside the housing distant from and in parallel to the substrate, an encapsulant at least partly filling the interior of the housing and covering the substrate and the printed circuit board, and a heat protective layer arranged inside the housing between the substrate and the printed circuit board, and extending in a plane that is parallel to the substrate and the printed circuit board. A thermal resistance of the heat protective layer is greater than a thermal resistance of the encapsulant.

公开(公告)号：US11004764B2

公开(公告)日：2021-05-11

申请号：US16519802

申请日：2019-07-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Tao Hong ,  Tino Karczewski ,  Matthias Lassmann ,  Christian Schweikert

IPC: H01L21/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/492 ,  H01L23/373 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/433

Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.

公开(公告)号：US20200035579A1

公开(公告)日：2020-01-30

申请号：US16519802

申请日：2019-07-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Tao Hong ,  Tino Karczewski ,  Matthias Lassmann ,  Christian Schweikert

IPC: H01L23/367 ,  H01L23/492 ,  H01L23/373 ,  H01L23/495 ,  H01L23/433 ,  H01L29/16 ,  H01L23/31 ,  H01L21/56 ,  H01L21/52

Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.