公开(公告)号：US20230369256A1

公开(公告)日：2023-11-16

申请号：US17742767

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Kushal Kshirsagar ,  Eung San Cho ,  Danny Clavette ,  Wenkang Huang ,  Angela Kessler

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/13 ,  H05K1/11 ,  H05K3/30 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/3675 ,  H01L23/13 ,  H05K1/111 ,  H05K3/301 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49872 ,  H05K2201/10431 ,  H05K2201/1003

Abstract: A semiconductor assembly includes a carrier including a dielectric substrate and a plurality of contact pads disposed on an upper surface of the carrier, first and second surface mount packages mounted on the carrier, first and second discrete inductors respectively mounted over the first and second surface mount packages, wherein the first and second surface mount packages each comprise lower surface terminals that face and electrically connect with the contact pads from the carrier, wherein the first and second surface mount packages each comprise an upper side that faces away from the carrier, and wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages.

公开(公告)号：US20230369160A1

公开(公告)日：2023-11-16

申请号：US17742666

申请日：2022-05-12

Applicant: Infineon Technologies AG

Inventor： Kushal Kshirsagar ,  Eung San Cho ,  Arun Kumar Gnanappa ,  Wenkang Huang ,  Angela Kessler ,  Marcel Rene Mueller ,  Stephen Pullen

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: A semiconductor assembly includes a device carrier that includes a dielectric core region and a plurality of contact pads disposed on an upper surface, a semiconductor device package having a plurality of lower surface terminals, a discrete passive element comprising a main body and a pair of leads, and a region of gap filler material, wherein the semiconductor device package is mounted on the device carrier with the lower surface terminals facing and electrically connected to a group of the contact pads, wherein the discrete passive element is mounted on the device carrier with the pair of leads electrically connecting with contact surfaces on the device carrier, and wherein the region of gap filler material is arranged between a lower surface of the main body and the upper surface of the semiconductor device package and thermally couples the semiconductor device package to the discrete passive element.