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公开(公告)号：US11469164B2
公开(公告)日：2022-10-11
申请号：US16744967
申请日：2020-01-16
Applicant: Infineon Technologies AG
Inventor： Robert Fehler , Eung San Cho , Danny Clavette , Petteri Palm
IPC: H01L23/48 , H01L23/12 , H01L23/34 , H01L21/00 , H05K7/00 , H05K1/18 , H05K7/10 , H05K7/18 , H01L23/495 , H01L25/07 , H01L23/00
Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.
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公开(公告)号：US11183934B2
公开(公告)日：2021-11-23
申请号：US16655295
申请日：2019-10-17
Applicant: Infineon Technologies AG
Inventor： Danny Clavette
Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.
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Patent Agency Ranking
公开(公告)号：US20230369256A1
公开(公告)日：2023-11-16
申请号：US17742767
申请日：2022-05-12
Applicant: Infineon Technologies AG
Inventor： Kushal Kshirsagar , Eung San Cho , Danny Clavette , Wenkang Huang , Angela Kessler
IPC: H01L23/66 , H01L23/367 , H01L23/13 , H05K1/11 , H05K3/30 , H01L23/495 , H01L23/498
CPC classification number: H01L23/66 , H01L23/3675 , H01L23/13 , H05K1/111 , H05K3/301 , H01L23/49503 , H01L23/49541 , H01L23/49872 , H05K2201/10431 , H05K2201/1003
Abstract: A semiconductor assembly includes a carrier including a dielectric substrate and a plurality of contact pads disposed on an upper surface of the carrier, first and second surface mount packages mounted on the carrier, first and second discrete inductors respectively mounted over the first and second surface mount packages, wherein the first and second surface mount packages each comprise lower surface terminals that face and electrically connect with the contact pads from the carrier, wherein the first and second surface mount packages each comprise an upper side that faces away from the carrier, and wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages.
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公开(公告)号：US20240030820A1
公开(公告)日：2024-01-25
申请号：US17870405
申请日：2022-07-21
Applicant: Infineon Technologies AG
Inventor： Angela Kessler , Eung San Cho , Danny Clavette
CPC classification number: H02M3/1584 , H02M3/157 , H02M3/33571
Abstract: A power semiconductor module arrangement includes a circuit carrier including an electrically insulating substrate and an upper metallization layer disposed on upper side of the electrically insulating substrate, and a plurality of power stage inlays that each include first and second transistor dies and a driver die configured to control switching of the first and second transistor dies. Each of the power stage inlays are modular units comprising terminals that are electrically connected to the first and second transistor dies and the driver die. Each of the power stage inlays is embedded within the electrically insulating substrate. The upper metallization layer comprises conductive connectors that extend over the power stage inlays and connect with the terminals of the terminals of each of the power stage inlays.
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公开(公告)号：US11817786B2
公开(公告)日：2023-11-14
申请号：US17508078
申请日：2021-10-22
Applicant: Infineon Technologies AG
Inventor： Danny Clavette
CPC classification number: H02M3/1582 , H01L27/0203 , H01L27/0629 , H01L27/0676
Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.
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公开(公告)号：US20210119542A1
公开(公告)日：2021-04-22
申请号：US16655295
申请日：2019-10-17
Applicant: Infineon Technologies AG
Inventor： Danny Clavette
IPC: H02M3/158
Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current. The high-current power required by the processor is constrained within the package substrate.
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公开(公告)号：US20210225745A1
公开(公告)日：2021-07-22
申请号：US16744967
申请日：2020-01-16
Applicant: Infineon Technologies AG
Inventor： Robert Fehler , Eung San Cho , Danny Clavette , Petteri Palm
IPC: H01L23/495 , H01L25/07 , H01L23/00
Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.
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