公开(公告)号：US10186481B2

公开(公告)日：2019-01-22

申请号：US15459270

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Frank Daeche ,  Zeeshan Umar

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/552 ,  H01F17/00 ,  H01L23/498 ,  H01L23/538 ,  H02M3/158

Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.

公开(公告)号：US20170271260A1

公开(公告)日：2017-09-21

申请号：US15459270

申请日：2017-03-15

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Frank Daeche ,  Zeeshan Umar

IPC: H01L23/522 ,  H02M3/158 ,  H01L23/552

CPC classification number: H01L23/5227 ,  H01F17/00 ,  H01F17/0013 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/552 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2924/181 ,  H02M3/158 ,  H01L2924/00012

Abstract: A device includes a semiconductor chip, a plurality of planar metallization layers arranged over a main surface of the semiconductor chip, and a passive component including windings, wherein each of the windings is formed in one of the plurality of planar metallization layers.