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公开(公告)号：US20170063235A1
公开(公告)日：2017-03-02
申请号：US15347951
申请日：2016-11-10
IPC分类号： H02M3/158
CPC分类号： H02M3/158 , H02M3/156 , H02M3/1584 , H02M3/1588 , H02M2003/1566 , Y02B70/1466
摘要： A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
摘要翻译： 控制电路可以被配置为接收指示电源的输出电压与输出电压的期望设定值之间的差异的误差信号。 根据一种配置，根据误差信号，控制电路在脉冲宽度调制模式下启动操作控制电路之间的切换，并以脉冲频率调制模式操作控制电路以产生输出电压。 在瞬态状态下，例如当动态负载瞬时需要不同电流量时，在脉冲频率调制模式下的控制电路的操作使得电源能够通过动态负载来满足电流消耗。 在瞬态条件之后，控制电路切换回以脉宽调制方式工作。
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公开(公告)号：US10707160B2
公开(公告)日：2020-07-07
申请号：US15817712
申请日：2017-11-20
发明人： Robert T. Carroll
IPC分类号： H01L23/498 , H01L23/495 , H01L23/00 , H01L21/48 , H01L21/768 , H01L23/482 , H01L23/50 , H01L27/06 , H01L29/423 , H02M3/335 , H01L27/088 , H02M3/158
摘要： According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
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公开(公告)号：US10483193B2
公开(公告)日：2019-11-19
申请号：US16247941
申请日：2019-01-15
IPC分类号： H05K5/02 , H05K7/18 , H01L23/495 , H01L21/50 , H01L23/482 , H01L23/532 , H01L23/00 , H01L21/48 , H01L27/088
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
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公开(公告)号：US20190148272A1
公开(公告)日：2019-05-16
申请号：US16247941
申请日：2019-01-15
IPC分类号： H01L23/495 , H01L21/48 , H01L23/482 , H01L23/532 , H01L23/00 , H01L21/50
CPC分类号： H01L23/49562 , H01L21/4825 , H01L21/50 , H01L23/4824 , H01L23/49575 , H01L23/53228 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L27/088 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/97 , H01L2924/1305 , H01L2924/1306 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2924/00
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
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公开(公告)号：US10044270B2
公开(公告)日：2018-08-07
申请号：US15347951
申请日：2016-11-10
摘要： A control circuitry can be configured to receive an error signal indicating a difference between an output voltage of the power supply and a desired setpoint for the output voltage. According to one configuration, depending on the error signal, the control circuitry initiates switching between operating the control circuitry in a pulse width modulation mode and operating the control circuitry in a pulse frequency modulation mode to produce an output voltage. Operation of the control circuitry in the pulse frequency modulation mode during a transient condition, such as when a dynamic load instantaneously requires a different amount of current, enables the power supply to satisfy current consumption by the dynamic load. Subsequent to the transient condition, the control circuitry switches back to operation in the pulse width modulation mode.
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公开(公告)号：US10224266B2
公开(公告)日：2019-03-05
申请号：US15193573
申请日：2016-06-27
IPC分类号： H01L23/495 , H01L21/48 , H01L23/532 , H01L21/50 , H01L23/482 , H01L23/00 , H01L27/088
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
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公开(公告)号：US20180076124A1
公开(公告)日：2018-03-15
申请号：US15817712
申请日：2017-11-20
发明人： Robert T. Carroll
IPC分类号： H01L23/498 , H02M3/337 , H01L21/48 , H02M3/335 , H01L21/768 , H01L23/482 , H01L23/495 , H01L23/50 , H01L23/00 , H01L27/06 , H01L49/02 , H01L29/423 , H01L27/088
摘要： According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.
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公开(公告)号：US20160307828A1
公开(公告)日：2016-10-20
申请号：US15193573
申请日：2016-06-27
IPC分类号： H01L23/495 , H01L21/48 , H01L23/532
CPC分类号： H01L23/49562 , H01L21/4825 , H01L21/50 , H01L23/4824 , H01L23/49575 , H01L23/53228 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/97 , H01L27/088 , H01L2224/131 , H01L2224/13147 , H01L2224/16245 , H01L2224/97 , H01L2924/1305 , H01L2924/1306 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2924/00
摘要： According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
摘要翻译： 根据这里的示例性配置，引线框架包括第一导电条，第二导电条和基本相邻并基本上彼此平行设置的第三导电条。 半导体芯片衬底包括与第二阵列开关电路相邻并平行设置的第一开关电路阵列。 第一阵列的开关电路中的源节点被设置为基本上与第二阵列的开关电路中的源节点相邻并且基本上平行。 当半导体芯片和引线框架装置组合以形成电路封装时，电路封装件中的半导体芯片与导电条之间的连接接口将第一阵列的开关电路中的每个源节点与多个源节点 在第二阵列的开关电路中到引线框装置中的公共导电条。
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