公开(公告)号：US11580367B2

公开(公告)日：2023-02-14

申请号：US16079525

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zidong Du ,  Qi Guo ,  Tianshi Chen ,  Yunji Chen

IPC: G06N3/06 ,  G06F7/57 ,  G06F15/78 ,  G06N3/04 ,  G06N3/063

Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.

公开(公告)号：US10684946B2

公开(公告)日：2020-06-16

申请号：US16070735

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Qi Guo ,  Tianshi Chen ,  Yunji Chen

IPC: G06F12/02 ,  G06F12/12 ,  G06F12/06 ,  G06F12/123

Abstract: A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.

公开(公告)号：US20190026246A1

公开(公告)日：2019-01-24

申请号：US16071458

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Tianshi Chen ,  Zidong Du ,  Qi Guo ,  Yunji Chen

IPC: G06F15/78 ,  G06F3/06

Abstract: The present invention is directed to the storage technical field and discloses an on-chip data partitioning read-write method, the method comprises: a data partitioning step for storing on-chip data in different areas, and storing the on-chip data in an on-chip storage medium and an off-chip storage medium respectively, based on a data partitioning strategy; a pre-operation step for performing an operational processing of an on-chip address index of the on-chip storage data in advance when implementing data splicing; and a data splicing step, for splicing the on-chip storage data and the off-chip input data to obtain a representation of the original data based on a data splicing strategy. Also provided are a corresponding on-chip data partitioning read-write system and device. Thus, read and write of repeated data can be efficiently realized, reducing memory access bandwidth requirements while providing good flexibility, thus reducing on-chip storage overhead.

公开(公告)号：US20190026626A1

公开(公告)日：2019-01-24

申请号：US16071801

申请日：2016-08-09

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zidong Du ,  Qi Guo ,  Tianshi Chen ,  Yunji Chen

IPC: G06N3/063 ,  G06F7/575

Abstract: A neural network accelerator and an operation method thereof applicable in the field of neural network algorithms are disclosed. The neural network accelerator comprises an on-chip storage medium for storing data externally transmitted or for storing data generated during computing; an on-chip address index module for mapping to a correct storage address on the basis of an input index when an operation is performed; a core computing module for performing a neural network operation; and a multi-ALU device for obtaining input data from the core computing module or the on-chip storage medium to perform a nonlinear operation which cannot be completed by the core computing module. By introducing a multi -ALU design into the neural network accelerator, an operation speed of the nonlinear operation is increased, such that the neural network accelerator is more efficient.