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1.发明申请公开(公告)号：US20210075639A1
公开(公告)日：2021-03-11
申请号：US17100570
申请日：2020-11-20
Inventor： Jinhua Tao , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/44 , H04L12/761 , H04L12/933
Abstract: The present invention provides a fractal tree structure-based data transmit device and method, a control device, and an intelligent chip. The device comprises: a central node that is as a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; the plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data; the central node, the forwarder modules and the plurality of leaf nodes are connected in the fractal tree network structure, and the central node is directly connected to M the forwarder modules and/or leaf nodes, any the forwarder module is directly connected to M the next level forwarder modules and/or leaf nodes.
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2.发明授权公开(公告)号：US10904034B2
公开(公告)日：2021-01-26
申请号：US15781608
申请日：2016-06-17
Inventor： Jinhua Tao , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/44 , H04L12/761 , H04L12/933
Abstract: One example of a device comprises: a central node that is as a communication data center of a network-on-chip; a plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes, the central node is individually in communication connection with each group of leaf nodes by means of the forwarder module, a communication structure constituted by each group of leaf nodes has self-similarity, and the plurality of leaf nodes are in communication connection with the central node in a complete multi-way tree approach by means of the forwarder modules of multiple levels.
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3.发明授权公开(公告)号：US11616662B2
公开(公告)日：2023-03-28
申请号：US17100570
申请日：2020-11-20
Inventor： Jinhua Tao , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/44 , H04L45/16 , H04L49/109
Abstract: The present invention provides a fractal tree structure-based data transmit device and method, a control device, and an intelligent chip. The device comprises: a central node that is as a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; the plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data; the central node, the forwarder modules and the plurality of leaf nodes are connected in the fractal tree network structure, and the central node is directly connected to M the forwarder modules and/or leaf nodes, any the forwarder module is directly connected to M the next level forwarder modules and/or leaf nodes.
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4.发明授权公开(公告)号：US11488000B2
公开(公告)日：2022-11-01
申请号：US15770457
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure provides an operation apparatus and method for an acceleration chip for accelerating a deep neural network algorithm. The apparatus comprises: a vector addition processor module and a vector function value arithmetic unit and a vector multiplier-adder module wherein the three modules execute a programmable instruction, and interact with each other to calculate values of neurons and a network output result of a neural network, and a variation amount of a synaptic weight representing the interaction strength of the neurons on an input layer to the neurons on an output layer; and the three modules are all provided with an intermediate value storage region and perform read and write operations on a primary memory.
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公开(公告)号：US20180329681A1
公开(公告)日：2018-11-15
申请号：US15773959
申请日：2016-06-17
Inventor： Shijin Zhang , Tao Luo , Shaoli Liu , Yunji Chen
Abstract: The present disclosure provides a quick operation device for a nonlinear function, and a method therefor. The device comprises: a domain conversion part for converting an input independent variable into a corresponding value in a table lookup range; a table lookup part for looking up a slope and an intercept of the corresponding piecewise linear fitting based on the input independent variable or an independent variable processed by the domain conversion part; and a linear fitting part for obtaining, a final result in a way of linear fitting based on the slope and the intercept obtained, by means of table lookup, by the table lookup part. The present disclosure solves the problems of slow operation speed, large area of the operation device, and high power consumption caused by the traditional method.
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Patent Agency Ranking
公开(公告)号：US20190026626A1
公开(公告)日：2019-01-24
申请号：US16071801
申请日：2016-08-09
Inventor： Zidong Du , Qi Guo , Tianshi Chen , Yunji Chen
Abstract: A neural network accelerator and an operation method thereof applicable in the field of neural network algorithms are disclosed. The neural network accelerator comprises an on-chip storage medium for storing data externally transmitted or for storing data generated during computing; an on-chip address index module for mapping to a correct storage address on the basis of an input index when an operation is performed; a core computing module for performing a neural network operation; and a multi-ALU device for obtaining input data from the core computing module or the on-chip storage medium to perform a nonlinear operation which cannot be completed by the core computing module. By introducing a multi -ALU design into the neural network accelerator, an operation speed of the nonlinear operation is increased, such that the neural network accelerator is more efficient.
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公开(公告)号：US11580367B2
公开(公告)日：2023-02-14
申请号：US16079525
申请日：2016-08-09
Inventor： Zidong Du , Qi Guo , Tianshi Chen , Yunji Chen
Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.
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公开(公告)号：US10805233B2
公开(公告)日：2020-10-13
申请号：US15781686
申请日：2016-06-17
Inventor： Huiying Lan , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/911 , G06F15/173 , H04L12/44 , H04L12/755 , H04L12/933
Abstract: A communication structure comprises: a central node that is a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; a plurality of leaf nodes that are communication data nodes of the network-on-chip and used for transmitting the communication data to the central node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes, the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules, the communication structure is a fractal-tree structure, the communication structure constituted by each group of leaf nodes has self-similarity, and the forwarder modules comprises a central forwarder module, leaf forwarder modules, and intermediate forwarder modules.
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公开(公告)号：US10416964B2
公开(公告)日：2019-09-17
申请号：US15773974
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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公开(公告)号：US20180321911A1
公开(公告)日：2018-11-08
申请号：US15773974
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Lou , Cheng Qian , Yunji Chen , Tianshi Chen
CPC classification number: G06F7/50 , G06F7/501 , G06F7/509 , G06F2207/4824 , G06N3/063 , G06N3/08 , G06N5/003
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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