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1.发明授权公开(公告)号：US11488000B2
公开(公告)日：2022-11-01
申请号：US15770457
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure provides an operation apparatus and method for an acceleration chip for accelerating a deep neural network algorithm. The apparatus comprises: a vector addition processor module and a vector function value arithmetic unit and a vector multiplier-adder module wherein the three modules execute a programmable instruction, and interact with each other to calculate values of neurons and a network output result of a neural network, and a variation amount of a synaptic weight representing the interaction strength of the neurons on an input layer to the neurons on an output layer; and the three modules are all provided with an intermediate value storage region and perform read and write operations on a primary memory.
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公开(公告)号：US11580367B2
公开(公告)日：2023-02-14
申请号：US16079525
申请日：2016-08-09
Inventor： Zidong Du , Qi Guo , Tianshi Chen , Yunji Chen
Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.
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公开(公告)号：US10416964B2
公开(公告)日：2019-09-17
申请号：US15773974
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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Patent Agency Ranking
公开(公告)号：US20180321911A1
公开(公告)日：2018-11-08
申请号：US15773974
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Lou , Cheng Qian , Yunji Chen , Tianshi Chen
CPC classification number: G06F7/50 , G06F7/501 , G06F7/509 , G06F2207/4824 , G06N3/063 , G06N3/08 , G06N5/003
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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公开(公告)号：US20190026626A1
公开(公告)日：2019-01-24
申请号：US16071801
申请日：2016-08-09
Inventor： Zidong Du , Qi Guo , Tianshi Chen , Yunji Chen
Abstract: A neural network accelerator and an operation method thereof applicable in the field of neural network algorithms are disclosed. The neural network accelerator comprises an on-chip storage medium for storing data externally transmitted or for storing data generated during computing; an on-chip address index module for mapping to a correct storage address on the basis of an input index when an operation is performed; a core computing module for performing a neural network operation; and a multi-ALU device for obtaining input data from the core computing module or the on-chip storage medium to perform a nonlinear operation which cannot be completed by the core computing module. By introducing a multi -ALU design into the neural network accelerator, an operation speed of the nonlinear operation is increased, such that the neural network accelerator is more efficient.
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公开(公告)号：US10684946B2
公开(公告)日：2020-06-16
申请号：US16070735
申请日：2016-08-09
Inventor： Qi Guo , Tianshi Chen , Yunji Chen
IPC: G06F12/02 , G06F12/12 , G06F12/06 , G06F12/123
Abstract: A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.
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公开(公告)号：US10379816B2
公开(公告)日：2019-08-13
申请号：US15773973
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure provides a data accumulation device and method, and a digital signal processing device. The device comprises: an accumulation tree module for accumulating input data in the form of a binary tree structure and outputting accumulated result data; a register module including a plurality of groups of registers and used for registering intermediate data generated by the accumulation tree module during an accumulation process and the accumulated result data; and a control circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated, and generating a flag signal to perform the following control: selecting a result obtained after adding one or more of intermediate data stored in the register to the accumulated result as output data, or directly selecting the accumulated result as output data. Thus, a plurality of groups of input data can be rapidly accumulated to a group of sums in a clock cycle. At the same time, the accumulation device can flexibly select to simultaneously accumulate some data of the plurality of input data by means of a control signal.
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公开(公告)号：US20190026246A1
公开(公告)日：2019-01-24
申请号：US16071458
申请日：2016-08-09
Inventor： Tianshi Chen , Zidong Du , Qi Guo , Yunji Chen
Abstract: The present invention is directed to the storage technical field and discloses an on-chip data partitioning read-write method, the method comprises: a data partitioning step for storing on-chip data in different areas, and storing the on-chip data in an on-chip storage medium and an off-chip storage medium respectively, based on a data partitioning strategy; a pre-operation step for performing an operational processing of an on-chip address index of the on-chip storage data in advance when implementing data splicing; and a data splicing step, for splicing the on-chip storage data and the off-chip input data to obtain a representation of the original data based on a data splicing strategy. Also provided are a corresponding on-chip data partitioning read-write system and device. Thus, read and write of repeated data can be efficiently realized, reducing memory access bandwidth requirements while providing good flexibility, thus reducing on-chip storage overhead.
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