公开(公告)号：US11488000B2

公开(公告)日：2022-11-01

申请号：US15770457

申请日：2016-06-17

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zhen Li ,  Shaoli Liu ,  Shijin Zhang ,  Tao Luo ,  Cheng Qian ,  Yunji Chen ,  Tianshi Chen

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F17/16

Abstract: The present disclosure provides an operation apparatus and method for an acceleration chip for accelerating a deep neural network algorithm. The apparatus comprises: a vector addition processor module and a vector function value arithmetic unit and a vector multiplier-adder module wherein the three modules execute a programmable instruction, and interact with each other to calculate values of neurons and a network output result of a neural network, and a variation amount of a synaptic weight representing the interaction strength of the neurons on an input layer to the neurons on an output layer; and the three modules are all provided with an intermediate value storage region and perform read and write operations on a primary memory.

公开(公告)号：US10416964B2

公开(公告)日：2019-09-17

申请号：US15773974

申请日：2016-06-17

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zhen Li ,  Shaoli Liu ,  Shijin Zhang ,  Tao Luo ,  Cheng Qian ,  Yunji Chen ,  Tianshi Chen

IPC: G06F7/509 ,  G06F7/50 ,  G06N3/06 ,  G06F7/501 ,  G06N3/08

Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.

公开(公告)号：US20180321911A1

公开(公告)日：2018-11-08

申请号：US15773974

申请日：2016-06-17

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zhen Li ,  Shaoli Liu ,  Shijin Zhang ,  Tao Lou ,  Cheng Qian ,  Yunji Chen ,  Tianshi Chen

IPC: G06F7/50 ,  G06F7/501

CPC classification number: G06F7/50 ,  G06F7/501 ,  G06F7/509 ,  G06F2207/4824 ,  G06N3/063 ,  G06N3/08 ,  G06N5/003

Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.

公开(公告)号：US10379816B2

公开(公告)日：2019-08-13

申请号：US15773973

申请日：2016-06-17

Applicant: Institute of Computing Technology, Chinese Academy of Sciences

Inventor： Zhen Li ,  Shaoli Liu ,  Shijin Zhang ,  Tao Luo ,  Cheng Qian ,  Yunji Chen ,  Tianshi Chen

IPC: G06F7/509 ,  G06F16/22 ,  G06F7/50

Abstract: The present disclosure provides a data accumulation device and method, and a digital signal processing device. The device comprises: an accumulation tree module for accumulating input data in the form of a binary tree structure and outputting accumulated result data; a register module including a plurality of groups of registers and used for registering intermediate data generated by the accumulation tree module during an accumulation process and the accumulated result data; and a control circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated, and generating a flag signal to perform the following control: selecting a result obtained after adding one or more of intermediate data stored in the register to the accumulated result as output data, or directly selecting the accumulated result as output data. Thus, a plurality of groups of input data can be rapidly accumulated to a group of sums in a clock cycle. At the same time, the accumulation device can flexibly select to simultaneously accumulate some data of the plurality of input data by means of a control signal.