公开(公告)号：US09431955B1

公开(公告)日：2016-08-30

申请号：US14985689

申请日：2015-12-31

Applicant: Integrated Device Technology, Inc.

Inventor： James Bryan Northcutt ,  Eugene Stanley Trefethen ,  Harry LeRoy Sutter ,  Stephen Amar Tibbitts ,  Charles Michael Rice ,  Bruce Edward Clark

IPC: H03B5/04 ,  H03B5/32 ,  H03H9/10 ,  H03H9/13 ,  H03H9/205

CPC classification number: G01R31/2884 ,  G01R31/282 ,  G01R31/2836 ,  G01R31/2853 ,  H03B5/04 ,  H03B5/32 ,  H03B5/36 ,  H03H9/02133 ,  H03H9/02834 ,  H03H9/02897 ,  H03H9/0547 ,  H03H9/10 ,  H03H9/1021 ,  H03H9/13 ,  H03H9/205 ,  H03H11/44

Abstract: An integrated circuit device includes a pair of serially-connected crystal resonators arranged as a first crystal resonator, which is configured to preferentially support a fundamental resonance mode in response to an input signal, and a second crystal resonator, which is configured to preferentially support a third or higher overtone resonance mode in response to a signal generated at an output terminal of the first crystal resonator. A negative impedance converter (NIC) is also provided, which has an input terminal electrically connected to an input terminal of the first crystal resonator and an output terminal electrically connected to one of the output terminal of the first crystal resonator and the output terminal of the second crystal resonator. The NIC may be a CMOS-based NIC that is devoid of inductive reactance from a passive inductor.

Abstract translation: 集成电路器件包括一对串联连接的晶体谐振器，被布置为第一晶体谐振器，其被配置为优先支持响应于输入信号的基本谐振模式;以及第二晶体谐振器，其被配置为优先支持 响应于在第一晶体谐振器的输出端产生的信号而产生第三或更高泛音谐振模式。 还提供了一种负阻抗转换器（NIC），其具有电连接到第一晶体谐振器的输入端子的输入端子和电连接到第一晶体谐振器的输出端子和输出端子的输出端子 第二个晶体谐振器。 NIC可能是基于CMOS的NIC，没有来自无源电感的感抗。

公开(公告)号：US09791503B1

公开(公告)日：2017-10-17

申请号：US14871411

申请日：2015-09-30

Applicant: Integrated Device Technology, Inc.

Inventor： James Bryan Northcutt ,  Stephen Amar Tibbitts ,  Robert A. Gubser ,  Bruce Edward Clark ,  John William Fallisgaard ,  Kenneth Astrof

IPC: G01R31/3187 ,  G01R31/28 ,  H03B5/32

CPC classification number: G01R31/2884 ,  G01R31/282 ,  G01R31/2836 ,  G01R31/2853 ,  H03B5/04 ,  H03B5/32 ,  H03B5/36 ,  H03H9/02133 ,  H03H9/02834 ,  H03H9/02897 ,  H03H9/0547 ,  H03H9/10 ,  H03H9/1021 ,  H03H9/13 ,  H03H9/205 ,  H03H11/44

Abstract: Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test operations may occur during a built-in self-test time interval when the oscillator circuit is at least partially disabled. In this manner, built-in self-test circuitry may be utilized to provide an efficient means of testing a resonating element/structure using circuitry that is integrated within an oscillator chip and within a wafer-level chip-scale package (WLCSP) containing the resonator.