公开(公告)号：US10367494B2

公开(公告)日：2019-07-30

申请号：US16155023

申请日：2018-10-09

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03K5/19 ,  H03K19/21 ,  G01R23/02

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.

公开(公告)号：US20190044504A1

公开(公告)日：2019-02-07

申请号：US16155023

申请日：2018-10-09

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03K5/19 ,  H03K19/21

CPC classification number: H03K5/19 ,  H03K19/21

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.

公开(公告)号：US20180212598A1

公开(公告)日：2018-07-26

申请号：US15468352

申请日：2017-03-24

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03K5/19 ,  H03K19/21

CPC classification number: H03K5/19 ,  H03K19/21

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.

公开(公告)号：US10211843B2

公开(公告)日：2019-02-19

申请号：US15798726

申请日：2017-10-31

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03L7/06 ,  H03L7/095 ,  H03L7/089

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.

公开(公告)号：US10135431B2

公开(公告)日：2018-11-20

申请号：US15468352

申请日：2017-03-24

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: G01R23/02 ,  H03K5/19 ,  H03K19/21

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.

公开(公告)号：US20180054208A1

公开(公告)日：2018-02-22

申请号：US15798726

申请日：2017-10-31

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03L7/095 ,  H03L7/089

CPC classification number: H03L7/095 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.

公开(公告)号：US09831882B1

公开(公告)日：2017-11-28

申请号：US15226286

申请日：2016-08-02

Applicant: Integrated Device Technology, Inc.

Inventor： Xinqing Chen ,  HaiQi Liu ,  Yuan Zhang

IPC: H03L7/06 ,  H03L7/095 ,  H03L7/089

CPC classification number: H03L7/095 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

Abstract: The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.