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公开(公告)号：US10367494B2
公开(公告)日：2019-07-30
申请号：US16155023
申请日：2018-10-09
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.
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2.发明授权Single-ended signal equalization with a programmable 1-tap decision feedback equalizer 有权具有可编程1点抽头决策反馈均衡器的单端信号均衡公开(公告)号：US09542991B1
公开(公告)日：2017-01-10
申请号：US15079370
申请日：2016-03-24
Applicant: Integrated Device Technology, Inc.
IPC: G11C5/14 , G11C11/4091 , G11C11/4076 , G11C11/4093 , G11C11/4074
CPC classification number: G11C11/4093 , G11C5/04 , G11C5/145 , G11C5/147 , G11C7/02 , G11C7/1072 , G11C7/109 , G11C11/4074 , G11C11/4076
Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) receive a sequence of input values that have been carried on a single-ended line of a data bus coupled to a memory channel, (ii) slice a previous input value of said sequence of input values to generate a previous output value, (iii) slice a current input value of said sequence of input values to generate a current output value, and (iv) present said current output value on a differential line. The previous input value generally precedes said current input value in said sequence of input values. The second circuit may be configured to decode said previous input value based on a tap coefficient value to generate a plurality of feedback values suitable to reduce an inter-symbol interference in said current input value caused by said previous input value.
Abstract translation: 一种装置包括第一电路和第二电路。 第一电路可以被配置为（i）接收已经在耦合到存储器通道的数据总线的单端行上承载的输入值序列，（ii）切片所述输入值序列的先前输入值 以产生先前的输出值，（iii）对所述输入值序列的当前输入值进行切片以产生电流输出值，以及（iv）在差分线上呈现所述当前输出值。 先前的输入值通常在所述输入值序列中的所述当前输入值之前。 第二电路可以被配置为基于抽头系数值对所述先前输入值进行解码，以生成适合于减少由所述先前输入值引起的所述当前输入值中的符号间干扰的多个反馈值。
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公开(公告)号：US20190044504A1
公开(公告)日：2019-02-07
申请号：US16155023
申请日：2018-10-09
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a waveform in response to a frequency of an input clock signal and a threshold frequency. The second circuit may be configured to generate a control signal in response to a type of the waveform. The type of the waveform may comprise at least one of pulses and a steady state. The control signal may have a first state when the type of the waveform is the pulses and a second state when the type of the waveform is the steady state. A width of the pulses may be based on the threshold frequency.
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公开(公告)号：US20180212598A1
公开(公告)日：2018-07-26
申请号：US15468352
申请日：2017-03-24
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.
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Patent Agency Ranking
公开(公告)号：US20180054208A1
公开(公告)日：2018-02-22
申请号：US15798726
申请日：2017-10-31
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
CPC classification number: H03L7/095 , H03L7/087 , H03L7/0891 , H03L7/18
Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.
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公开(公告)号：US09831882B1
公开(公告)日：2017-11-28
申请号：US15226286
申请日：2016-08-02
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
CPC classification number: H03L7/095 , H03L7/087 , H03L7/0891 , H03L7/18
Abstract: The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the comparisons are within a pre-determined threshold. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active.
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公开(公告)号：US10211843B2
公开(公告)日：2019-02-19
申请号：US15798726
申请日：2017-10-31
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to (i) receive pulses generated in response to a comparison of a feedback signal and a reference signal, (ii) filter the pulses when a frequency of the feedback signal is close to a frequency of the reference signal and (iii) generate an enable signal in response to the filtered pulses. The digital circuit may be configured to generate an output signal representing a lock status between (i) the feedback signal and (ii) the reference signal. The lock status may be determined (a) during a decision window based on a number of pulses of the reference signal and (b) when the enable signal is active (B) the decision window may be repeated periodically until the enable signal is not active.
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公开(公告)号：US10135431B2
公开(公告)日：2018-11-20
申请号：US15468352
申请日：2017-03-24
Applicant: Integrated Device Technology, Inc.
Inventor： Xinqing Chen , HaiQi Liu , Yuan Zhang
Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input clock signal operating at a frequency. The first circuit may modify the input clock signal according to a threshold frequency to generate a waveform for the intermediate signal. The waveform of the intermediate signal may have at least one of (i) pulses and (ii) a steady state. The second circuit may be configured to generate a control signal in response to the intermediate signal. The second circuit may modify the intermediate signal to generate the control signal. The control signal may have a first state when the intermediate signal has pulses. The control signal may have a second state when the intermediate signal has the steady state.
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公开(公告)号：US09589626B1
公开(公告)日：2017-03-07
申请号：US14993271
申请日：2016-01-12
Applicant: Integrated Device Technology, Inc.
Inventor： HaiQi Liu , Yue Yu , Yumin Zhang , Yi Xie
IPC: G11C7/10 , G11C11/4074 , G11C11/4093 , G11C7/22
CPC classification number: G11C11/4074 , G11C5/04 , G11C5/148 , G11C7/1006 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C11/4093
Abstract: An apparatus having a first circuit and a second circuit. The first circuit may be configured to buffer an input signal received as a single-ended signal from a data bus connected between a memory channel and a memory controller. The second circuit may be configured to condition the input signal relative to a reference voltage to generate a differential signal. The reference voltage may be isolated from the second circuit in response to a transition from a power down condition to a power on condition.
Abstract translation: 一种具有第一电路和第二电路的装置。 第一电路可以被配置为缓冲从连接在存储器通道和存储器控制器之间的数据总线作为单端信号接收的输入信号。 第二电路可以被配置为相对于参考电压调节输入信号以产生差分信号。 响应于从断电状态到电源接通状态的转变，参考电压可以与第二电路隔离。
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