公开(公告)号：US20250046680A1

公开(公告)日：2025-02-06

申请号：US18921373

申请日：2024-10-21

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20230197574A1

公开(公告)日：2023-06-22

申请号：US18111329

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5385 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/09 ,  H01L24/83 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16237

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.

公开(公告)号：US20210272881A1

公开(公告)日：2021-09-02

申请号：US17323840

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Aditya S. VAIDYA ,  Ravindranath V. MAHAJAN ,  Digvijay A. RAORANE ,  Paul R. START

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H01L25/065

Abstract: An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.