公开(公告)号：US20200235249A1

公开(公告)日：2020-07-23

申请号：US16650321

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Kinyip PHOA ,  Justin S. SANDFORD ,  Junjun WAN ,  Akm A. AHSAN ,  Leif R. PAULSON ,  Bernhard SELL

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/8605

Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

公开(公告)号：US20230317720A1

公开(公告)日：2023-10-05

申请号：US18207065

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Guannan LIU ,  Akm A. AHSAN ,  Mark ARMSTRONG ,  Bernhard SELL

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/0705 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/16 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L27/0886 ,  H01L21/823456

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20200243517A1

公开(公告)日：2020-07-30

申请号：US16257855

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Guannan LIU ,  Akm A. AHSAN ,  Mark ARMSTRONG ,  Bernhard SELL

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.