公开(公告)号：US20220329248A1

公开(公告)日：2022-10-13

申请号：US17842585

申请日：2022-06-16

Applicant: Intel Corporation

Inventor： Ali Azam ,  Ashoke Ravi ,  Ofir Degani

IPC: H03L7/197 ,  H03L7/081 ,  H03L7/091 ,  H03L7/093

Abstract: For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.

公开(公告)号：US12255653B2

公开(公告)日：2025-03-18

申请号：US17356564

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Ali Azam ,  Ashoke Ravi ,  Benjamin Jann

IPC: H03K5/00 ,  G06F7/68 ,  H03K5/02

Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.