公开(公告)号：US20240145450A1

公开(公告)日：2024-05-02

申请号：US18050527

申请日：2022-10-28

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Amit JAIN ,  Sameer SHEKHAR

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/562

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.

公开(公告)号：US20190146569A1

公开(公告)日：2019-05-16

申请号：US16230440

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Chee Lim NGE ,  Amit JAIN ,  Anant DEVAL ,  Nimrod ANGEL ,  Fabrice PAILLET ,  Michael ZELIKSON ,  Sergio Carlo RODRIGUEZ

IPC: G06F1/3206 ,  H02M3/158 ,  H02M1/08 ,  G06F1/3296 ,  G06F1/20

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

公开(公告)号：US20240355778A1

公开(公告)日：2024-10-24

申请号：US18758909

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Amit JAIN

IPC: H01L25/065 ,  H01L23/427 ,  H01L23/552 ,  H03H1/00 ,  H03H7/01

CPC classification number: H01L25/0652 ,  H01L23/427 ,  H01L23/552 ,  H01L28/10 ,  H01L28/60 ,  H03H1/0007 ,  H03H7/0115 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06544 ,  H01L2225/06589 ,  H03H2001/0078

Abstract: Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

公开(公告)号：US20210398944A1

公开(公告)日：2021-12-23

申请号：US16910014

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Sameer SHEKHAR ,  Amit JAIN

IPC: H01L25/065 ,  H01L23/427 ,  H01L23/552 ,  H01L49/02 ,  H03H1/00 ,  H03H7/01

Abstract: Embodiments disclosed herein include electronic packages and their components. In an embodiment, an electronic package comprises a package substrate and a base die over the package substrate. In an embodiment, the electronic package further comprises a plurality of chiplets over the base die. In an embodiment, the base die comprises a substrate, a first metal layer and a second metal layer between the substrate and the plurality of chiplets, and a third metal layer and a fourth metal layer between the package substrate and the substrate. In an embodiment, a filter is integrated into one or more layers of the base die.

公开(公告)号：US20210384135A1

公开(公告)日：2021-12-09

申请号：US16987440

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Chin Lee KUAN ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG ,  Sameer SHEKHAR ,  Amit JAIN

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.