公开(公告)号：US11355427B2

公开(公告)日：2022-06-07

申请号：US16095916

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Sujit Sharan ,  Tin Poay Chuah ,  Ananth Prabhakumar

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18 ,  H01L25/065

Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

公开(公告)号：US11264338B2

公开(公告)日：2022-03-01

申请号：US15934191

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Ananth Prabhakumar ,  Krishna Srinivasan ,  Arnab Sarkar

IPC: H01L23/00 ,  H01L23/525 ,  H01L23/498 ,  H01L23/64

Abstract: Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.