公开(公告)号：US20170371779A1

公开(公告)日：2017-12-28

申请号：US15195328

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Andrea D'alessandro ,  Pranav Kalavade ,  Violante Moschiano

IPC: G06F12/02 ,  G11C16/04 ,  G06F11/07 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F2212/2022 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5644

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.

公开(公告)号：US09852065B1

公开(公告)日：2017-12-26

申请号：US15195328

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Andrea D'alessandro ,  Pranav Kalavade ,  Violante Moschiano

IPC: G11C16/04 ,  G06F12/02 ,  G11C16/10 ,  G11C16/26 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F11/073 ,  G06F11/076 ,  G06F2212/2022 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2211/5644

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing host, the write request to specify data to be written to the NAND flash memory; perform a number of program loops to program the data into a plurality of cells of the NAND flash memory, wherein a program loop comprises application of a program voltage to a wordline of the memory to change the threshold voltage of at least one cell of the plurality of cells; and wherein the number of program loops is to be determined prior to receipt of the write request and based on a distribution of threshold voltages of the cells or determined based on tracking a number of program errors for only a portion of the plurality of cells.