公开(公告)号：US20230137812A1

公开(公告)日：2023-05-04

申请号：US18092298

申请日：2022-12-31

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160103788A1

公开(公告)日：2016-04-14

申请号：US14975323

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160103787A1

公开(公告)日：2016-04-14

申请号：US14975292

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F15/80 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract translation: 根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数 。 处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且 将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。

公开(公告)号：US20160103789A1

公开(公告)日：2016-04-14

申请号：US14975327

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F15/80 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160103786A1

公开(公告)日：2016-04-14

申请号：US14975222

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20210406026A1

公开(公告)日：2021-12-30

申请号：US17316680

申请日：2021-05-10

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20190250921A1

公开(公告)日：2019-08-15

申请号：US16398183

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/1027 ,  G06F12/0875 ,  G06F13/42 ,  G06F15/80

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160110196A1

公开(公告)日：2016-04-21

申请号：US14976220

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160103790A1

公开(公告)日：2016-04-14

申请号：US14976228

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew T. FORSYTH ,  Brian J. HICKMANN ,  Jonathan C. HALL ,  Christopher J. HUGHES

IPC: G06F15/80 ,  G06F12/08 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.