Abstract:
Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.
Abstract:
Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.
Abstract:
In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
Abstract:
Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or more peripherals coupled to the power management module. The power management module may be configured to cause the one or more peripherals to delay operations based on determining that the cores are in a first power consumption state, and place the cores in a second power consumption state for a predetermined time period. The second power consumption state may consume less power than the first power consumption state. The power management module may cause the one or more peripherals to resume their operations based on expiration of the predetermined time period and may place the cores in a third power consumption state based on the expiration of the time period.
Abstract:
In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
Abstract:
In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.
Abstract:
In one embodiment, a processor comprises: a first domain including a plurality of cores; a second domain including at least one graphics engine; and a power controller including a first logic to receive a first performance request from a driver of the second domain and to determine a maximum operating frequency for the first domain responsive to the first performance request. Other embodiments are described and claimed.