公开(公告)号：US20240235545A9

公开(公告)日：2024-07-11

申请号：US17971619

申请日：2022-10-23

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

公开(公告)号：US20240137016A1

公开(公告)日：2024-04-25

申请号：US17971619

申请日：2022-10-22

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

公开(公告)号：US08993401B2

公开(公告)日：2015-03-31

申请号：US13927694

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

Abstract translation: 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。

公开(公告)号：US08681573B2

公开(公告)日：2014-03-25

申请号：US13870598

申请日：2013-04-25

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

IPC: G11C7/22

CPC classification number: G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

Abstract: Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

Abstract translation: 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

公开(公告)号：US09865695B2

公开(公告)日：2018-01-09

申请号：US14673163

申请日：2015-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/45 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

公开(公告)号：US20150206948A1

公开(公告)日：2015-07-23

申请号：US14673163

申请日：2015-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Chia-Hong Jan ,  Anisur Rahman

IPC: H01L29/45 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/45 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

Abstract translation: 一种装置包括具有金属栅极和漏极阱的第一器件，其经受在漏极阱和栅极之下的沟道之间的接点处的漏极接触电压从10V降低至4-6V的串联电阻。 该装置包括设置在排水井上方和排水井上的层间电介质层（ILD0）和排水井中的自对准硅排放接头。 该设备还包括位于与低于第一设备的电压工作的第一设备不同的区域中的后续设备。