公开(公告)号：US10199091B2

公开(公告)日：2019-02-05

申请号：US15373048

申请日：2016-12-08

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C5/14 ,  G11C11/417 ,  G11C11/413 ,  G11C29/24 ,  G11C29/04 ,  G11C29/12 ,  G11C29/52 ,  G11C11/412 ,  G11C29/50

Abstract: An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.

公开(公告)号：US12243611B2

公开(公告)日：2025-03-04

申请号：US17856897

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Minki Cho ,  Daniel Nemiroff ,  Carlos Tokunaga ,  James W. Tschanz ,  Kah Meng Yeem ,  Yaxin Shui

IPC: G11C5/00

Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

公开(公告)号：US10122347B2

公开(公告)日：2018-11-06

申请号：US15477913

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C7/00 ,  G11C7/12 ,  H03K3/011 ,  H03K3/012 ,  G11C11/419 ,  G06F1/32

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

公开(公告)号：US10483961B2

公开(公告)日：2019-11-19

申请号：US15925396

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Minki Cho ,  Pascal Meinerzhagen ,  Muhammad Khellah

IPC: H03L5/00 ,  H03K17/16 ,  H03K17/284 ,  H03K17/10

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

公开(公告)号：US20240333289A1

公开(公告)日：2024-10-03

申请号：US18193861

申请日：2023-03-31

Applicant: intel Corporation

Inventor： Minki Cho ,  Balkaran Gill

IPC: H03K19/003 ,  H01L27/02

CPC classification number: H03K19/00315 ,  H01L27/0207

Abstract: The disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.

公开(公告)号：US20240005962A1

公开(公告)日：2024-01-04

申请号：US17856897

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Minki Cho ,  Daniel Nemiroff ,  Carlos Tokunaga ,  James W. Tschanz ,  Kah Meng Yeem ,  Yaxin Shui

IPC: G11C5/00

CPC classification number: G11C5/005

Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

公开(公告)号：US20190288681A1

公开(公告)日：2019-09-19

申请号：US15925396

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Suyoung Bang ,  Minki Cho ,  Pascal Meinerzhagen ,  Muhammad Khellah

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/284

Abstract: An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.

公开(公告)号：US20180191347A1

公开(公告)日：2018-07-05

申请号：US15394296

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Andrea Bonetti ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Minki Cho ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K19/0185 ,  H03K19/21

CPC classification number: H03K19/018521 ,  H03K19/21

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

公开(公告)号：US20240235545A9

公开(公告)日：2024-07-11

申请号：US17971619

申请日：2022-10-23

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

公开(公告)号：US20240137016A1

公开(公告)日：2024-04-25

申请号：US17971619

申请日：2022-10-22

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.