公开(公告)号：US20150074354A1

公开(公告)日：2015-03-12

申请号：US14541458

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Andrew T. Forsyth ,  Michael Abrash

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F15/8069 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/345 ,  G06F9/383 ,  G06F12/02 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028

Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

Abstract translation: 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。

公开(公告)号：US09495153B2

公开(公告)日：2016-11-15

申请号：US13844111

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

IPC: G06F9/312 ,  G06F9/302 ,  G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

公开(公告)号：US10042814B2

公开(公告)日：2018-08-07

申请号：US14541458

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Andrew T. Forsyth ,  Michael Abrash

IPC: G06F9/312 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/02 ,  G06F12/0875

Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.