公开(公告)号：US20160156355A1

公开(公告)日：2016-06-02

申请号：US15016260

申请日：2016-02-04

Applicant: Intel Corporation

Inventor： Arijit RAYCHOWDHURY ,  James W. TSCHANZ ,  Vivek DE

IPC: H03K19/177 ,  G11C11/16

CPC classification number: H03K19/17728 ,  G11C11/16 ,  H03K19/177

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。