公开(公告)号：US20200350817A1

公开(公告)日：2020-11-05

申请号：US16642853

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vivek DE ,  Krishnan RAVICHANDRAN ,  Harish KRISHNAMURTHY ,  Khondker AHMED ,  Sriram VANGAL ,  Vaibhav VAIDYA ,  Turbo MAJUMDER ,  Christopher SCHAEF ,  Suhwan KIM ,  Xiaosen LIU ,  Nachiket DESAI

IPC: H02M3/07

Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.

公开(公告)号：US20160156355A1

公开(公告)日：2016-06-02

申请号：US15016260

申请日：2016-02-04

Applicant: Intel Corporation

Inventor： Arijit RAYCHOWDHURY ,  James W. TSCHANZ ,  Vivek DE

IPC: H03K19/177 ,  G11C11/16

CPC classification number: H03K19/17728 ,  G11C11/16 ,  H03K19/177

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

公开(公告)号：US20210081017A1

公开(公告)日：2021-03-18

申请号：US16956447

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Jayanth M. DEVARAJU ,  Vivek DE ,  Sriram VANGAL

IPC: G06F1/3206 ,  G06F1/3296 ,  G06F1/324

Abstract: Circuitry is provided to control a performance level of a processing device depending on two or more operating points of the processing device. An operating point has a corresponding frequency and a corresponding voltage. The performance-level control circuitry arranged to cross-multiply parameters corresponding to a first operating point and a second, different operating point of the processing device. A relative energy expenditure of the first operating point and the second operating point is determined based on the cross multiplication. An operating point of the processing device is selected depending on the determined relative energy expenditure. An apparatus having the performance level control circuitry, machine readable instructions for implementing the performance level control and a corresponding method are also provided.