公开(公告)号：US12057836B2

公开(公告)日：2024-08-06

申请号：US17033342

申请日：2020-09-25

申请人： Intel Corporation

发明人： Sean R Atsatt ,  Arun Jangity ,  Thien Le ,  Simon Chong

IPC分类号： H03K19/177 ,  H03K3/037 ,  H03K19/17724 ,  H03K19/17736 ,  H03K19/1776

CPC分类号： H03K19/1776 ,  H03K3/037 ,  H03K19/17724 ,  H03K19/17736

摘要： Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

公开(公告)号：US20220113350A1

公开(公告)日：2022-04-14

申请号：US17559322

申请日：2021-12-22

申请人： Intel Corporation

发明人： Dheeraj Subbareddy ,  Arun Jangity ,  Ramya Yeluri ,  Mahesh K. Kumashikar ,  Atul Maheshwari ,  Ankireddy Nalamalpu

IPC分类号： G01R31/3177

摘要： Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.