公开(公告)号：US11960734B2

公开(公告)日：2024-04-16

申请号：US17033348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sean R Atsatt ,  Ilya K. Ganusov

IPC: G06F3/06 ,  G06N3/08 ,  H03K19/17724

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0673 ,  G06N3/08

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. A quasi-delay insensitive (QDI) shift register and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.

公开(公告)号：US12057836B2

公开(公告)日：2024-08-06

申请号：US17033342

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Sean R Atsatt ,  Arun Jangity ,  Thien Le ,  Simon Chong

IPC: H03K19/177 ,  H03K3/037 ,  H03K19/17724 ,  H03K19/17736 ,  H03K19/1776

CPC classification number: H03K19/1776 ,  H03K3/037 ,  H03K19/17724 ,  H03K19/17736

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.