公开(公告)号：US20210257036A1

公开(公告)日：2021-08-19

申请号：US16790074

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Tarek Ahmed Ameen Beshari ,  Narayanan Ramanan ,  Arun Thathachary ,  Shantanu Rajwade ,  Matin Amani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

公开(公告)号：US11094386B1

公开(公告)日：2021-08-17

申请号：US16790074

申请日：2020-02-13

Applicant: Intel Corporation

Inventor： Xiang Yang ,  Tarek Ahmed Ameen Beshari ,  Narayanan Ramanan ,  Arun Thathachary ,  Shantanu Rajwade ,  Matin Amani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C11/419

Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.