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1.发明申请公开(公告)号：US20230044991A1
公开(公告)日：2023-02-09
申请号：US17393877
申请日：2021-08-04
Applicant: Intel Corporation
Inventor： Shantanu Rajwade , Kartik Ganapathi , Rohit Shenoy , Kristopher Gaewsky , MarkAnthony Golez , Vivek Angoth , Pranav Kalavade , Sarvesh Gangadhar
IPC: G06F3/06
Abstract: Systems, apparatuses and methods may provide for technology that detects a request to program a NAND memory containing a plurality of dies and programs the NAND memory on a stripe-by-stripe basis, wherein each stripe spans the plurality of dies and includes multiple types of pages. The multiple types of pages may reduce program time variability across the stripes and reduce the error susceptibility of the NAND memory.
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公开(公告)号：US20220310160A1
公开(公告)日：2022-09-29
申请号：US17212792
申请日：2021-03-25
Applicant: Intel Corporation
Inventor： Ali Khakifirooz , Pranav Kalavade , Shantanu Rajwade , Tarek Ahmed Ameen Beshari
Abstract: Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.
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Patent Agency Ranking
公开(公告)号：US20210257036A1
公开(公告)日：2021-08-19
申请号：US16790074
申请日：2020-02-13
Applicant: Intel Corporation
Inventor： Xiang Yang , Tarek Ahmed Ameen Beshari , Narayanan Ramanan , Arun Thathachary , Shantanu Rajwade , Matin Amani
Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
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公开(公告)号：US11094386B1
公开(公告)日：2021-08-17
申请号：US16790074
申请日：2020-02-13
Applicant: Intel Corporation
Inventor： Xiang Yang , Tarek Ahmed Ameen Beshari , Narayanan Ramanan , Arun Thathachary , Shantanu Rajwade , Matin Amani
Abstract: Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.
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公开(公告)号：US20190043567A1
公开(公告)日：2019-02-07
申请号：US16115372
申请日：2018-08-28
Applicant: Intel Corporation
Inventor： Ali Khakifirooz , Shantanu Rajwade , Rohit Shenoy , Aliasgar Madraswala , Pranav Kalavade
Abstract: An apparatus and/or system is described including a memory device or a controller for a memory device to perform an adjustment of a read operation time for data stored in the memory device. In embodiments, the apparatus may receive a request for data stored in the memory device and a read operation time adjustment module operable by the controller may acquire a first operation temperature of the memory device, obtained at a time of programming of the data stored in the memory device. The apparatus may acquire a second operation temperature of the memory device, obtained after the request for the data stored in the memory device is received. Based at least partially on the first operation temperature and the second operation temperature, the apparatus may adjust the read operation time to read the data. Other embodiments are disclosed and claimed.
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公开(公告)号：US12211563B2
公开(公告)日：2025-01-28
申请号：US17411919
申请日：2021-08-25
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Archana Tankasala , Aliasgar S. Madraswala , Shantanu Rajwade
Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.
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公开(公告)号：US20230061293A1
公开(公告)日：2023-03-02
申请号：US17411919
申请日：2021-08-25
Applicant: Intel Corporation
Inventor： Sagar Upadhyay , Archana Tankasala , Aliasgar S. Madraswala , Shantanu Rajwade
Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.
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