公开(公告)号：US20240213026A1

公开(公告)日：2024-06-27

申请号：US18085768

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Matthew J. Prince ,  Lawrence Zaino ,  Barry B. Butler ,  Girish Sharma ,  Robert R. Mitchell ,  Rajaram A. Pai ,  Niels Sveum ,  Alison V. Davis ,  Chun Chen Kuo ,  Reza Bayati ,  Swapnadip Ghosh

IPC: H01L21/28 ,  B24B37/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  B24B37/04 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. An example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. Conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. A top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.