公开(公告)号：US20240213100A1

公开(公告)日：2024-06-27

申请号：US18087879

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Chiao-ti Huang ,  Bishwajit Debnath ,  Anupama Bowonder ,  Matthew J. Prince

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823878 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L24/16 ,  H01L2224/16225

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. The gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. The inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.

公开(公告)号：US20240332088A1

公开(公告)日：2024-10-03

申请号：US18129617

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Swapnadip Ghosh ,  Chiao-Ti Huang ,  Matthew Prince ,  Jeffrey Miles Tan ,  Ramy Ghostine ,  Anupama Bowonder

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823456 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: One or more transistors may have gate structures with differing sidewall slopes. The gate structures may be over stacks of channel regions in nanosheets (or nanoribbons or nanowires), and the differing gate profiles may correspond to differing electrical characteristics. Transistors with metal gate structures may be tuned by strategically etching the gate structures, for example, using lower etch powers, higher etch temperatures, and/or longer etch durations, to achieve substantially vertical gate profiles.

公开(公告)号：US20240113105A1

公开(公告)日：2024-04-04

申请号：US17937212

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Alison V. Davis ,  Bern Youngblood ,  Reza Bayati ,  Swapnadip Ghosh ,  Matthew J. Prince ,  Jeffrey Miles Tan

IPC: H01L27/088 ,  H01L21/762 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5× difference in width) but substantially the same height (e.g., less than 5 nm difference in height). A given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. According to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. Using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.

公开(公告)号：US20240105453A1

公开(公告)日：2024-03-28

申请号：US17953873

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Matthew J. Prince ,  Alison V. Davis ,  Ramy Ghostine ,  Piyush M. Sinha ,  Oleg Golonzka ,  Swapnadip Ghosh ,  Manish Sharma

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater, such as 10:1). In an example, a semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The semiconductor region can be, for example, a fin of semiconductor material that extends between a source region and a drain region, or one or more nanowires or nanoribbons of semiconductor material that extend between a source region and a drain region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A particular plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio so as to enable densely integrated devices.

公开(公告)号：US20240213026A1

公开(公告)日：2024-06-27

申请号：US18085768

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Matthew J. Prince ,  Lawrence Zaino ,  Barry B. Butler ,  Girish Sharma ,  Robert R. Mitchell ,  Rajaram A. Pai ,  Niels Sveum ,  Alison V. Davis ,  Chun Chen Kuo ,  Reza Bayati ,  Swapnadip Ghosh

IPC: H01L21/28 ,  B24B37/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  B24B37/04 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. An example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. Conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. A top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.

公开(公告)号：US20240112916A1

公开(公告)日：2024-04-04

申请号：US17936934

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Reza Bayati

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. Conductive contacts formed over the source and drain regions along a source/drain trench. The gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. The contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. Accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.

公开(公告)号：US20240222447A1

公开(公告)日：2024-07-04

申请号：US18090048

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Reken Patel ,  Conor P. Puls ,  Krishna Ganesan ,  Akitomo Matsubayashi ,  Diana Ivonne Paredes ,  Sunzida Ferdous ,  Brian Greene ,  Lateef Uddin Syed ,  Kyle T. Horak ,  Lin Hu ,  Anupama Bowonder ,  Swapnadip Ghosh ,  Amritesh Rai ,  Shruti Subramanian ,  Gordon S. Freeman

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.

公开(公告)号：US20240203739A1

公开(公告)日：2024-06-20

申请号：US18083064

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Matthew J. Prince ,  Alison V. Davis ,  Chun Chen Kuo ,  Andrew Arnold ,  Cun Wen

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. Some of the gate cuts may be at least 2× wider than others. Such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.